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[185.176.79.56]) by mx.google.com with ESMTPS id r7-20020a056000014700b0032339bf4a8dsi6990189wrx.837.2023.10.12.07.49.07 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Oct 2023 07:49:08 -0700 (PDT) Received-SPF: pass (google.com: domain of jonathan.cameron@huawei.com designates 185.176.79.56 as permitted sender) client-ip=185.176.79.56; Authentication-Results: mx.google.com; spf=pass (google.com: domain of jonathan.cameron@huawei.com designates 185.176.79.56 as permitted sender) smtp.mailfrom=jonathan.cameron@huawei.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4S5svw17w8z687hF; Thu, 12 Oct 2023 22:48:44 +0800 (CST) Received: from localhost (10.202.227.76) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Thu, 12 Oct 2023 15:49:05 +0100 Date: Thu, 12 Oct 2023 15:49:04 +0100 From: Jonathan Cameron To: Salil Mehta CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH V5 5/9] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Message-ID: <20231012154904.0000728e@Huawei.com> In-Reply-To: <20231011194355.15628-6-salil.mehta@huawei.com> References: <20231011194355.15628-1-salil.mehta@huawei.com> <20231011194355.15628-6-salil.mehta@huawei.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.227.76] X-ClientProxiedBy: lhrpeml500002.china.huawei.com (7.191.160.78) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected X-TUID: XX4JeY/DkKre On Wed, 11 Oct 2023 20:43:51 +0100 Salil Mehta wrote: > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on > PCI and is IO port based and hence existing CPUs AML code assumes _CRS objects > would evaluate to a system resource which describes IO Port address. But on ARM > arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence > _CRS object should evaluate to system resource which describes memory-mapped > base address. Update build CPUs AML function to accept both IO/MEMORY region > spaces and accordingly update the _CRS object. > > Legacy CPU Hotplug uses Generic ACPI GPE Block Bit 2 (GPE.2) event handler to > notify OSPM about any CPU hot(un)plug events. GED framework uses new register > interface for cpu-(ctrl)dev. Make AML for GPE.2 event handler conditional. > > Co-developed-by: Keqian Zhu > Signed-off-by: Keqian Zhu > Signed-off-by: Salil Mehta > Reviewed-by: Gavin Shan > Tested-by: Vishnu Pajjuri Reviewed-by: Jonathan Cameron From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4053ACDB46E for ; Thu, 12 Oct 2023 14:49:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qqx0O-0004e2-Dg; Thu, 12 Oct 2023 10:49:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qqx06-0004aw-RI; Thu, 12 Oct 2023 10:49:22 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qqwzz-0007xQ-EJ; Thu, 12 Oct 2023 10:49:21 -0400 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4S5svw17w8z687hF; Thu, 12 Oct 2023 22:48:44 +0800 (CST) Received: from localhost (10.202.227.76) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Thu, 12 Oct 2023 15:49:05 +0100 Date: Thu, 12 Oct 2023 15:49:04 +0100 To: Salil Mehta CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH V5 5/9] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Message-ID: <20231012154904.0000728e@Huawei.com> In-Reply-To: <20231011194355.15628-6-salil.mehta@huawei.com> References: <20231011194355.15628-1-salil.mehta@huawei.com> <20231011194355.15628-6-salil.mehta@huawei.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.227.76] X-ClientProxiedBy: lhrpeml500002.china.huawei.com (7.191.160.78) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 11 Oct 2023 20:43:51 +0100 Salil Mehta wrote: > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on > PCI and is IO port based and hence existing CPUs AML code assumes _CRS objects > would evaluate to a system resource which describes IO Port address. But on ARM > arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence > _CRS object should evaluate to system resource which describes memory-mapped > base address. Update build CPUs AML function to accept both IO/MEMORY region > spaces and accordingly update the _CRS object. > > Legacy CPU Hotplug uses Generic ACPI GPE Block Bit 2 (GPE.2) event handler to > notify OSPM about any CPU hot(un)plug events. GED framework uses new register > interface for cpu-(ctrl)dev. Make AML for GPE.2 event handler conditional. > > Co-developed-by: Keqian Zhu > Signed-off-by: Keqian Zhu > Signed-off-by: Salil Mehta > Reviewed-by: Gavin Shan > Tested-by: Vishnu Pajjuri Reviewed-by: Jonathan Cameron