From: Jakub Kicinski <kuba@kernel.org>
To: Srujana Challa <schalla@marvell.com>
Cc: <herbert@gondor.apana.org.au>, <davem@davemloft.net>,
<linux-crypto@vger.kernel.org>, <bbrezillon@kernel.org>,
<arno@natisbad.org>, <ndabilpuram@marvell.com>
Subject: Re: [PATCH 03/10] crypto: octeontx2: add devlink option to set max_rxc_icb_cnt
Date: Mon, 16 Oct 2023 07:02:00 -0700 [thread overview]
Message-ID: <20231016070200.6f18ede4@kernel.org> (raw)
In-Reply-To: <20231016064934.1913964-4-schalla@marvell.com>
On Mon, 16 Oct 2023 12:19:27 +0530 Srujana Challa wrote:
> On CN10KA B0/CN10KB HW, maximum icb entries that RX can use,
> can be configured through HW CSR. This patch adds option
> to set max icb entries through devlink parameter and also sets
> max_rxc_icb_cnt to 0xc0 as default to match inline
> inbound peak performance compared to other chip versions.
If it's a resource it should be configured via devlink-resource.
Every piece of devlink config must be documented under Documentation/
When you repost please CC netdev.
next prev parent reply other threads:[~2023-10-16 14:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-16 6:49 [PATCH 00/10] Add Marvell CN10KB/CN10KA B0 support Srujana Challa
2023-10-16 6:49 ` [PATCH 01/10] crypto: octeontx2: remove CPT block reset Srujana Challa
2023-10-16 6:49 ` [PATCH 02/10] crypto: octeontx2: add SGv2 support for CN10KB or CN10KA B0 Srujana Challa
2023-10-16 6:49 ` [PATCH 03/10] crypto: octeontx2: add devlink option to set max_rxc_icb_cnt Srujana Challa
2023-10-16 14:02 ` Jakub Kicinski [this message]
2023-10-21 6:46 ` kernel test robot
2023-10-16 6:49 ` [PATCH 04/10] crypto: octeontx2: add devlink option to set t106 mode Srujana Challa
2023-10-21 10:03 ` kernel test robot
2023-10-16 6:49 ` [PATCH 05/10] crypto: octeontx2: remove errata workaround for CN10KB or CN10KA B0 chip Srujana Challa
2023-10-16 6:49 ` [PATCH 06/10] crypto: octeontx2: add LF reset on queue disable Srujana Challa
2023-10-16 6:49 ` [PATCH 07/10] octeontx2-af: update CPT inbound inline IPsec mailbox Srujana Challa
2023-10-16 6:49 ` [PATCH 08/10] crypto: octeontx2: add ctx_val workaround Srujana Challa
2023-10-16 6:49 ` [PATCH 09/10] crypto/octeontx2: register error interrupts for inline cptlf Srujana Challa
2023-10-16 6:49 ` [PATCH 10/10] crypto: octeontx2: support setting ctx ilen for inline CPT LF Srujana Challa
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231016070200.6f18ede4@kernel.org \
--to=kuba@kernel.org \
--cc=arno@natisbad.org \
--cc=bbrezillon@kernel.org \
--cc=davem@davemloft.net \
--cc=herbert@gondor.apana.org.au \
--cc=linux-crypto@vger.kernel.org \
--cc=ndabilpuram@marvell.com \
--cc=schalla@marvell.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.