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Mon, 16 Oct 2023 10:07:14 -0700 (PDT) Received: from thinkpad ([117.207.31.199]) by smtp.gmail.com with ESMTPSA id s14-20020a170902ea0e00b001c9b5b63e36sm8718097plg.32.2023.10.16.10.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 10:07:13 -0700 (PDT) Date: Mon, 16 Oct 2023 22:37:06 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Minghuan Lian , Mingkai Hu , Roy Zang , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , open list , imx@lists.linux.dev Subject: Re: [PATCH 3/3] PCI: layerscape: add suspend/resume for ls1043a Message-ID: <20231016170706.GG39962@thinkpad> References: <20230915184306.2374670-1-Frank.Li@nxp.com> <20230915184306.2374670-3-Frank.Li@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230915184306.2374670-3-Frank.Li@nxp.com> On Fri, Sep 15, 2023 at 02:43:06PM -0400, Frank Li wrote: > ls1043a add suspend/resume support. > Same comment as previous patch for patch description. > Signed-off-by: Frank Li > --- > drivers/pci/controller/dwc/pci-layerscape.c | 91 ++++++++++++++++++++- > 1 file changed, 90 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > index bc5a8ff1a26ce..debabb9bb41f4 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape.c > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > @@ -41,10 +41,20 @@ > #define SCFG_PEXSFTRSTCR 0x190 > #define PEXSR(idx) BIT(idx) > > +/* LS1043A PEX PME control register */ > +#define SCFG_PEXPMECR 0x144 > +#define PEXPME(idx) BIT(31 - (idx) * 4) > + > +/* LS1043A PEX LUT debug register */ > +#define LS_PCIE_LDBG 0x7fc > +#define LDBG_SR BIT(30) > +#define LDBG_WE BIT(31) > + > #define PCIE_IATU_NUM 6 > > struct ls_pcie_drvdata { > const u32 pf_off; > + const u32 lut_off; > const struct dw_pcie_host_ops *ops; > void (*exit_from_l2)(struct dw_pcie_rp *pp); > bool pm_support; > @@ -54,6 +64,7 @@ struct ls_pcie { > struct dw_pcie *pci; > const struct ls_pcie_drvdata *drvdata; > void __iomem *pf_base; > + void __iomem *lut_base; > struct regmap *scfg; > int index; > bool big_endian; > @@ -116,6 +127,23 @@ static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) > iowrite32(val, pcie->pf_base + off); > } > > +static u32 ls_pcie_lut_readl(struct ls_pcie *pcie, u32 off) > +{ Looking at ls_pcie_pf_{readl/writel} you can use a common function that does the read/write and pass the relevant base/offset. This will avoid code duplication. > + if (pcie->big_endian) > + return ioread32be(pcie->lut_base + off); > + > + return ioread32(pcie->lut_base + off); > +} > + > +static void ls_pcie_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) > +{ > + if (pcie->big_endian) > + iowrite32be(val, pcie->lut_base + off); > + else > + iowrite32(val, pcie->lut_base + off); > +} > + Remove extra newline > + > static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -249,6 +277,54 @@ static int ls1021a_pcie_host_init(struct dw_pcie_rp *pp) > return ret; > } > > +static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + u32 val; > + > + if (!pcie->scfg) { > + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); > + return; > + } > + > + /* Send Turn_off message */ > + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); If the register offset is the only difference, then you could pass the register offset via drvdata and use the same functions. > + val |= PEXPME(pcie->index); > + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); > + > + /* There are not register to check ACK, so wait PCIE_PME_TO_L2_TIMEOUT_US */ > + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); > + > + /* Clear Turn_off message */ > + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); > + val &= ~PEXPME(pcie->index); > + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); > +} > + > +static void ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + u32 val; > + Again, a comment here would be useful. - Mani > + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); > + val |= LDBG_WE; > + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); > + > + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); > + val |= LDBG_SR; > + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); > + > + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); > + val &= ~LDBG_SR; > + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); > + > + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); > + val &= ~LDBG_WE; > + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); > +} > + > static const struct dw_pcie_host_ops ls_pcie_host_ops = { > .host_init = ls_pcie_host_init, > .pme_turn_off = ls_pcie_send_turnoff_msg, > @@ -265,6 +341,18 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { > .exit_from_l2 = ls1021a_pcie_exit_from_l2, > }; > > +static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = { > + .host_init = ls1021a_pcie_host_init, /* the same as ls1021 */ > + .pme_turn_off = ls1043a_pcie_send_turnoff_msg, > +}; > + > +static const struct ls_pcie_drvdata ls1043a_drvdata = { > + .lut_off = 0x10000, > + .pm_support = true, > + .ops = &ls1043a_pcie_host_ops, > + .exit_from_l2 = ls1043a_pcie_exit_from_l2, > +}; > + > static const struct ls_pcie_drvdata layerscape_drvdata = { > .pf_off = 0xc0000, > .pm_support = true, > @@ -275,7 +363,7 @@ static const struct of_device_id ls_pcie_of_match[] = { > { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, > { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, > { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, > - { .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata }, > + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, > { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, > { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, > { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, > @@ -314,6 +402,7 @@ static int ls_pcie_probe(struct platform_device *pdev) > pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); > > pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; > + pcie->lut_base = pci->dbi_base + pcie->drvdata->lut_off; > > if (!ls_pcie_is_bridge(pcie)) > return -ENODEV; > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79431CDB474 for ; Mon, 16 Oct 2023 17:08:09 +0000 (UTC) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=dZSVRUDw; dkim-atps=neutral Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4S8Npw0flPz3vXc for ; Tue, 17 Oct 2023 04:08:08 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; 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Mon, 16 Oct 2023 10:07:14 -0700 (PDT) Received: from thinkpad ([117.207.31.199]) by smtp.gmail.com with ESMTPSA id s14-20020a170902ea0e00b001c9b5b63e36sm8718097plg.32.2023.10.16.10.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 10:07:13 -0700 (PDT) Date: Mon, 16 Oct 2023 22:37:06 +0530 From: Manivannan Sadhasivam To: Frank Li Subject: Re: [PATCH 3/3] PCI: layerscape: add suspend/resume for ls1043a Message-ID: <20231016170706.GG39962@thinkpad> References: <20230915184306.2374670-1-Frank.Li@nxp.com> <20230915184306.2374670-3-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230915184306.2374670-3-Frank.Li@nxp.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , imx@lists.linux.dev, Rob Herring , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Lorenzo Pieralisi , open list , Minghuan Lian , "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Roy Zang , Bjorn Helgaas , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Mingkai Hu Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, Sep 15, 2023 at 02:43:06PM -0400, Frank Li wrote: > ls1043a add suspend/resume support. > Same comment as previous patch for patch description. > Signed-off-by: Frank Li > --- > drivers/pci/controller/dwc/pci-layerscape.c | 91 ++++++++++++++++++++- > 1 file changed, 90 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > index bc5a8ff1a26ce..debabb9bb41f4 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape.c > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > @@ -41,10 +41,20 @@ > #define SCFG_PEXSFTRSTCR 0x190 > #define PEXSR(idx) BIT(idx) > > +/* LS1043A PEX PME control register */ > +#define SCFG_PEXPMECR 0x144 > +#define PEXPME(idx) BIT(31 - (idx) * 4) > + > +/* LS1043A PEX LUT debug register */ > +#define LS_PCIE_LDBG 0x7fc > +#define LDBG_SR BIT(30) > +#define LDBG_WE BIT(31) > + > #define PCIE_IATU_NUM 6 > > struct ls_pcie_drvdata { > const u32 pf_off; > + const u32 lut_off; > const struct dw_pcie_host_ops *ops; > void (*exit_from_l2)(struct dw_pcie_rp *pp); > bool pm_support; > @@ -54,6 +64,7 @@ struct ls_pcie { > struct dw_pcie *pci; > const struct ls_pcie_drvdata *drvdata; > void __iomem *pf_base; > + void __iomem *lut_base; > struct regmap *scfg; > int index; > bool big_endian; > @@ -116,6 +127,23 @@ static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) > iowrite32(val, pcie->pf_base + off); > } > > +static u32 ls_pcie_lut_readl(struct ls_pcie *pcie, u32 off) > +{ Looking at ls_pcie_pf_{readl/writel} you can use a common function that does the read/write and pass the relevant base/offset. This will avoid code duplication. > + if (pcie->big_endian) > + return ioread32be(pcie->lut_base + off); > + > + return ioread32(pcie->lut_base + off); > +} > + > +static void ls_pcie_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) > +{ > + if (pcie->big_endian) > + iowrite32be(val, pcie->lut_base + off); > + else > + iowrite32(val, pcie->lut_base + off); > +} > + Remove extra newline > + > static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -249,6 +277,54 @@ static int ls1021a_pcie_host_init(struct dw_pcie_rp *pp) > return ret; > } > > +static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + u32 val; > + > + if (!pcie->scfg) { > + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); > + return; > + } > + > + /* Send Turn_off message */ > + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); If the register offset is the only difference, then you could pass the register offset via drvdata and use the same functions. > + val |= PEXPME(pcie->index); > + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); > + > + /* There are not register to check ACK, so wait PCIE_PME_TO_L2_TIMEOUT_US */ > + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); > + > + /* Clear Turn_off message */ > + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); > + val &= ~PEXPME(pcie->index); > + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); > +} > + > +static void ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + u32 val; > + Again, a comment here would be useful. - Mani > + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); > + val |= LDBG_WE; > + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); > + > + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); > + val |= LDBG_SR; > + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); > + > + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); > + val &= ~LDBG_SR; > + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); > + > + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); > + val &= ~LDBG_WE; > + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); > +} > + > static const struct dw_pcie_host_ops ls_pcie_host_ops = { > .host_init = ls_pcie_host_init, > .pme_turn_off = ls_pcie_send_turnoff_msg, > @@ -265,6 +341,18 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { > .exit_from_l2 = ls1021a_pcie_exit_from_l2, > }; > > +static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = { > + .host_init = ls1021a_pcie_host_init, /* the same as ls1021 */ > + .pme_turn_off = ls1043a_pcie_send_turnoff_msg, > +}; > + > +static const struct ls_pcie_drvdata ls1043a_drvdata = { > + .lut_off = 0x10000, > + .pm_support = true, > + .ops = &ls1043a_pcie_host_ops, > + .exit_from_l2 = ls1043a_pcie_exit_from_l2, > +}; > + > static const struct ls_pcie_drvdata layerscape_drvdata = { > .pf_off = 0xc0000, > .pm_support = true, > @@ -275,7 +363,7 @@ static const struct of_device_id ls_pcie_of_match[] = { > { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, > { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, > { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, > - { .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata }, > + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, > { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, > { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, > { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, > @@ -314,6 +402,7 @@ static int ls_pcie_probe(struct platform_device *pdev) > pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); > > pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; > + pcie->lut_base = pci->dbi_base + pcie->drvdata->lut_off; > > if (!ls_pcie_is_bridge(pcie)) > return -ENODEV; > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 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Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , open list , imx@lists.linux.dev Subject: Re: [PATCH 3/3] PCI: layerscape: add suspend/resume for ls1043a Message-ID: <20231016170706.GG39962@thinkpad> References: <20230915184306.2374670-1-Frank.Li@nxp.com> <20230915184306.2374670-3-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230915184306.2374670-3-Frank.Li@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231016_100717_511240_22794BA0 X-CRM114-Status: GOOD ( 27.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: 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