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Tue, 17 Oct 2023 01:17:39 -0700 (PDT) Received: from thinkpad ([117.207.31.199]) by smtp.gmail.com with ESMTPSA id h16-20020a17090adb9000b002791d5a3e29sm769640pjv.6.2023.10.17.01.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 01:17:38 -0700 (PDT) Date: Tue, 17 Oct 2023 13:47:31 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Minghuan Lian , Mingkai Hu , Roy Zang , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , open list , imx@lists.linux.dev Subject: Re: [PATCH 2/3] PCI: layerscape: add suspend/resume for ls1021a Message-ID: <20231017081731.GD5274@thinkpad> References: <20230915184306.2374670-1-Frank.Li@nxp.com> <20230915184306.2374670-2-Frank.Li@nxp.com> <20231016165824.GF39962@thinkpad> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Mon, Oct 16, 2023 at 04:18:36PM -0400, Frank Li wrote: > On Mon, Oct 16, 2023 at 10:28:24PM +0530, Manivannan Sadhasivam wrote: > > On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote: > > > ls1021a add suspend/resume support. > > > > > > > Please add what the driver is doing during suspend/resume. > > > > > Signed-off-by: Frank Li > > > --- > > > drivers/pci/controller/dwc/pci-layerscape.c | 88 ++++++++++++++++++++- > > > 1 file changed, 87 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > > > index 20c48c06e2248..bc5a8ff1a26ce 100644 > > > --- a/drivers/pci/controller/dwc/pci-layerscape.c > > > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > > > @@ -35,6 +35,12 @@ > > > #define PF_MCR_PTOMR BIT(0) > > > #define PF_MCR_EXL2S BIT(1) > > > > > > +/* LS1021A PEXn PM Write Control Register */ > > > +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) > > > +#define PMXMTTURNOFF BIT(31) > > > +#define SCFG_PEXSFTRSTCR 0x190 > > > +#define PEXSR(idx) BIT(idx) > > > + > > > #define PCIE_IATU_NUM 6 > > > > > > struct ls_pcie_drvdata { > > > @@ -48,6 +54,8 @@ struct ls_pcie { > > > struct dw_pcie *pci; > > > const struct ls_pcie_drvdata *drvdata; > > > void __iomem *pf_base; > > > + struct regmap *scfg; > > > + int index; > > > bool big_endian; > > > }; > > > > > > @@ -170,13 +178,91 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) > > > return 0; > > > } > > > > > > +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > > > +{ > > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + struct ls_pcie *pcie = to_ls_pcie(pci); > > > + u32 val; > > > + > > > + if (!pcie->scfg) { > > > > Can this ever happen? > > > > > + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); > > > + return; > > > + } > > > + > > > + /* Send Turn_off message */ > > > > "Send PME_Turn_Off message" > > > > > + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); > > > + val |= PMXMTTURNOFF; > > > + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); > > > + > > > + /* There are not register to check ACK, so wait PCIE_PME_TO_L2_TIMEOUT_US */ > > > > "There is no specific register to check for PME_To_Ack from endpoint. So on the > > safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US." > > > > > + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); > > > + > > > + /* Clear Turn_off message */ > > > > "PME_Turn_off". But I'm not sure if this is really required. Are you doing it > > because the layerspace hw implements the PME_Turn_Off bit as "level triggered"? > > I am not sure how hardware implement this. But reference manual said: > > PMXMTTURNOFF: > Generate PM turnoff message for power management of PCI Express controllers. > This bit should be cleared by software. > 0 Clear PM turnoff (default) > 1 Trigger PM turnoff > Hmm, okay. Atleast add the below comment to make it understandable in the future: "Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit to complete the PME_Turn_Off handshake." - Mani > Frank > > > > > > + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); > > > + val &= ~PMXMTTURNOFF; > > > + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); > > > +} > > > + > > > +static void ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) > > > +{ > > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + struct ls_pcie *pcie = to_ls_pcie(pci); > > > + u32 val; > > > + > > > > A comment here would be good. > > > > > + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); > > > + val |= PEXSR(pcie->index); > > > + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); > > > + > > > + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); > > > + val &= ~PEXSR(pcie->index); > > > + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); > > > +} > > > + > > > +static int ls1021a_pcie_host_init(struct dw_pcie_rp *pp) > > > +{ > > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + struct ls_pcie *pcie = to_ls_pcie(pci); > > > + struct device *dev = pcie->pci->dev; > > > + u32 index[2]; > > > + int ret; > > > + > > > + ret = ls_pcie_host_init(pp); > > > + if (ret) > > > + return ret; > > > + > > > + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); > > > + if (IS_ERR(pcie->scfg)) { > > > + ret = PTR_ERR(pcie->scfg); > > > + dev_err(dev, "No syscfg phandle specified\n"); > > > + pcie->scfg = NULL; > > > + return ret; > > > + } > > > + > > > + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); > > > + if (ret) { > > > + pcie->scfg = NULL; > > > + return ret; > > > + } > > > + > > > + pcie->index = index[1]; > > > + > > > > The above syscon parsing could be done conditionally during probe itself. There > > is no need to do it during host_init() time. > > > > - Mani > > > > > + return ret; > > > +} > > > + > > > static const struct dw_pcie_host_ops ls_pcie_host_ops = { > > > .host_init = ls_pcie_host_init, > > > .pme_turn_off = ls_pcie_send_turnoff_msg, > > > }; > > > > > > +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { > > > + .host_init = ls1021a_pcie_host_init, > > > + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, > > > +}; > > > + > > > static const struct ls_pcie_drvdata ls1021a_drvdata = { > > > - .pm_support = false, > > > + .pm_support = true, > > > + .ops = &ls1021a_pcie_host_ops, > > > + .exit_from_l2 = ls1021a_pcie_exit_from_l2, > > > }; > > > > > > static const struct ls_pcie_drvdata layerscape_drvdata = { > > > -- > > > 2.34.1 > > > > > > > -- > > மணிவண்ணன் சதாசிவம் -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 784B8CDB474 for ; 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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , imx@lists.linux.dev, Rob Herring , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Lorenzo Pieralisi , open list , Minghuan Lian , "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Roy Zang , Bjorn Helgaas , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Mingkai Hu Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, Oct 16, 2023 at 04:18:36PM -0400, Frank Li wrote: > On Mon, Oct 16, 2023 at 10:28:24PM +0530, Manivannan Sadhasivam wrote: > > On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote: > > > ls1021a add suspend/resume support. > > > > > > > Please add what the driver is doing during suspend/resume. > > > > > Signed-off-by: Frank Li > > > --- > > > drivers/pci/controller/dwc/pci-layerscape.c | 88 ++++++++++++++++++++- > > > 1 file changed, 87 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > > > index 20c48c06e2248..bc5a8ff1a26ce 100644 > > > --- a/drivers/pci/controller/dwc/pci-layerscape.c > > > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > > > @@ -35,6 +35,12 @@ > > > #define PF_MCR_PTOMR BIT(0) > > > #define PF_MCR_EXL2S BIT(1) > > > > > > +/* LS1021A PEXn PM Write Control Register */ > > > +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) > > > +#define PMXMTTURNOFF BIT(31) > > > +#define SCFG_PEXSFTRSTCR 0x190 > > > +#define PEXSR(idx) BIT(idx) > > > + > > > #define PCIE_IATU_NUM 6 > > > > > > struct ls_pcie_drvdata { > > > @@ -48,6 +54,8 @@ struct ls_pcie { > > > struct dw_pcie *pci; > > > const struct ls_pcie_drvdata *drvdata; > > > void __iomem *pf_base; > > > + struct regmap *scfg; > > > + int index; > > > bool big_endian; > > > }; > > > > > > @@ -170,13 +178,91 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) > > > return 0; > > > } > > > > > > +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > > > +{ > > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + struct ls_pcie *pcie = to_ls_pcie(pci); > > > + u32 val; > > > + > > > + if (!pcie->scfg) { > > > > Can this ever happen? > > > > > + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); > > > + return; > > > + } > > > + > > > + /* Send Turn_off message */ > > > > "Send PME_Turn_Off message" > > > > > + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); > > > + val |= PMXMTTURNOFF; > > > + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); > > > + > > > + /* There are not register to check ACK, so wait PCIE_PME_TO_L2_TIMEOUT_US */ > > > > "There is no specific register to check for PME_To_Ack from endpoint. So on the > > safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US." > > > > > + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); > > > + > > > + /* Clear Turn_off message */ > > > > "PME_Turn_off". But I'm not sure if this is really required. Are you doing it > > because the layerspace hw implements the PME_Turn_Off bit as "level triggered"? > > I am not sure how hardware implement this. But reference manual said: > > PMXMTTURNOFF: > Generate PM turnoff message for power management of PCI Express controllers. > This bit should be cleared by software. > 0 Clear PM turnoff (default) > 1 Trigger PM turnoff > Hmm, okay. Atleast add the below comment to make it understandable in the future: "Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit to complete the PME_Turn_Off handshake." - Mani > Frank > > > > > > + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); > > > + val &= ~PMXMTTURNOFF; > > > + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); > > > +} > > > + > > > +static void ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) > > > +{ > > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + struct ls_pcie *pcie = to_ls_pcie(pci); > > > + u32 val; > > > + > > > > A comment here would be good. > > > > > + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); > > > + val |= PEXSR(pcie->index); > > > + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); > > > + > > > + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); > > > + val &= ~PEXSR(pcie->index); > > > + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); > > > +} > > > + > > > +static int ls1021a_pcie_host_init(struct dw_pcie_rp *pp) > > > +{ > > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + struct ls_pcie *pcie = to_ls_pcie(pci); > > > + struct device *dev = pcie->pci->dev; > > > + u32 index[2]; > > > + int ret; > > > + > > > + ret = ls_pcie_host_init(pp); > > > + if (ret) > > > + return ret; > > > + > > > + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); > > > + if (IS_ERR(pcie->scfg)) { > > > + ret = PTR_ERR(pcie->scfg); > > > + dev_err(dev, "No syscfg phandle specified\n"); > > > + pcie->scfg = NULL; > > > + return ret; > > > + } > > > + > > > + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); > > > + if (ret) { > > > + pcie->scfg = NULL; > > > + return ret; > > > + } > > > + > > > + pcie->index = index[1]; > > > + > > > > The above syscon parsing could be done conditionally during probe itself. There > > is no need to do it during host_init() time. > > > > - Mani > > > > > + return ret; > > > +} > > > + > > > static const struct dw_pcie_host_ops ls_pcie_host_ops = { > > > .host_init = ls_pcie_host_init, > > > .pme_turn_off = ls_pcie_send_turnoff_msg, > > > }; > > > > > > +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { > > > + .host_init = ls1021a_pcie_host_init, > > > + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, > > > +}; > > > + > > > static const struct ls_pcie_drvdata ls1021a_drvdata = { > > > - .pm_support = false, > > > + .pm_support = true, > > > + .ops = &ls1021a_pcie_host_ops, > > > + .exit_from_l2 = ls1021a_pcie_exit_from_l2, > > > }; > > > > > > static const struct ls_pcie_drvdata layerscape_drvdata = { > > > -- > > > 2.34.1 > > > > > > > -- > > மணிவண்ணன் சதாசிவம் -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org 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FOR FREESCALE LAYERSCAPE" , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , open list , imx@lists.linux.dev Subject: Re: [PATCH 2/3] PCI: layerscape: add suspend/resume for ls1021a Message-ID: <20231017081731.GD5274@thinkpad> References: <20230915184306.2374670-1-Frank.Li@nxp.com> <20230915184306.2374670-2-Frank.Li@nxp.com> <20231016165824.GF39962@thinkpad> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231017_011743_133708_1A689605 X-CRM114-Status: GOOD ( 36.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: 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