From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D613CDB483 for ; Tue, 17 Oct 2023 09:58:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qsgpQ-00023w-35; Tue, 17 Oct 2023 05:57:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qsgpM-000237-Ka; Tue, 17 Oct 2023 05:57:29 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qsgpJ-0006AC-1r; Tue, 17 Oct 2023 05:57:28 -0400 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4S8q8X69swz6K6GQ; Tue, 17 Oct 2023 17:54:52 +0800 (CST) Received: from localhost (10.202.227.76) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 17 Oct 2023 10:57:12 +0100 Date: Tue, 17 Oct 2023 10:57:11 +0100 To: Alistair Francis CC: , , , , , , , , , , Paolo Bonzini , , Alistair Francis Subject: Re: [PATCH v2 1/3] hw/pci: Add all Data Object Types defined in PCIe r6.0 Message-ID: <20231017105711.00001ed8@Huawei.com> In-Reply-To: <20231017052155.173577-2-alistair.francis@wdc.com> References: <20231017052155.173577-1-alistair.francis@wdc.com> <20231017052155.173577-2-alistair.francis@wdc.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.227.76] X-ClientProxiedBy: lhrpeml500003.china.huawei.com (7.191.162.67) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, 17 Oct 2023 15:21:53 +1000 Alistair Francis wrote: > Add all of the defined protocols/features from the PCIe-SIG r6.0 > "Table 6-32 PCI-SIG defined Data Object Types (Vendor ID = 0001h)" > table. > > Signed-off-by: Alistair Francis Reviewed-by: Jonathan Cameron If you feel like adding the PCIe r6.1 extras you could, but not necessary at this point though I can see they might become relevant fairly soon, particularly async messages and the connection ID stuff. > --- > include/hw/pci/pcie_doe.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/hw/pci/pcie_doe.h b/include/hw/pci/pcie_doe.h > index 87dc17dcef..15d94661f9 100644 > --- a/include/hw/pci/pcie_doe.h > +++ b/include/hw/pci/pcie_doe.h > @@ -46,6 +46,8 @@ REG32(PCI_DOE_CAP_STATUS, 0) > > /* PCI-SIG defined Data Object Types - r6.0 Table 6-32 */ > #define PCI_SIG_DOE_DISCOVERY 0x00 > +#define PCI_SIG_DOE_CMA 0x01 > +#define PCI_SIG_DOE_SECURED_CMA 0x02 > > #define PCI_DOE_DW_SIZE_MAX (1 << 18) > #define PCI_DOE_PROTOCOL_NUM_MAX 256 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qsgpO-00023L-5o for mharc-qemu-devel@gnu.org; Tue, 17 Oct 2023 05:57:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qsgpM-000237-Ka; Tue, 17 Oct 2023 05:57:29 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qsgpJ-0006AC-1r; Tue, 17 Oct 2023 05:57:28 -0400 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4S8q8X69swz6K6GQ; Tue, 17 Oct 2023 17:54:52 +0800 (CST) Received: from localhost (10.202.227.76) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 17 Oct 2023 10:57:12 +0100 Date: Tue, 17 Oct 2023 10:57:11 +0100 From: Jonathan Cameron To: Alistair Francis CC: , , , , , , , , , , Paolo Bonzini , , Alistair Francis Subject: Re: [PATCH v2 1/3] hw/pci: Add all Data Object Types defined in PCIe r6.0 Message-ID: <20231017105711.00001ed8@Huawei.com> In-Reply-To: <20231017052155.173577-2-alistair.francis@wdc.com> References: <20231017052155.173577-1-alistair.francis@wdc.com> <20231017052155.173577-2-alistair.francis@wdc.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.227.76] X-ClientProxiedBy: lhrpeml500003.china.huawei.com (7.191.162.67) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Oct 2023 09:57:29 -0000 Message-ID: <20231017095711.c1BacN3SYZ7PK617H90D_3p0emLanrvJ0UP_s1xQrRI@z> On Tue, 17 Oct 2023 15:21:53 +1000 Alistair Francis wrote: > Add all of the defined protocols/features from the PCIe-SIG r6.0 > "Table 6-32 PCI-SIG defined Data Object Types (Vendor ID = 0001h)" > table. > > Signed-off-by: Alistair Francis Reviewed-by: Jonathan Cameron If you feel like adding the PCIe r6.1 extras you could, but not necessary at this point though I can see they might become relevant fairly soon, particularly async messages and the connection ID stuff. > --- > include/hw/pci/pcie_doe.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/hw/pci/pcie_doe.h b/include/hw/pci/pcie_doe.h > index 87dc17dcef..15d94661f9 100644 > --- a/include/hw/pci/pcie_doe.h > +++ b/include/hw/pci/pcie_doe.h > @@ -46,6 +46,8 @@ REG32(PCI_DOE_CAP_STATUS, 0) > > /* PCI-SIG defined Data Object Types - r6.0 Table 6-32 */ > #define PCI_SIG_DOE_DISCOVERY 0x00 > +#define PCI_SIG_DOE_CMA 0x01 > +#define PCI_SIG_DOE_SECURED_CMA 0x02 > > #define PCI_DOE_DW_SIZE_MAX (1 << 18) > #define PCI_DOE_PROTOCOL_NUM_MAX 256