From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B778CC27C48 for ; Sat, 28 Oct 2023 08:56:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qwf5u-0000Nm-PR; Sat, 28 Oct 2023 04:54:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwf5t-0000Mz-5M for qemu-riscv@nongnu.org; Sat, 28 Oct 2023 04:54:57 -0400 Received: from mail-yw1-x112f.google.com ([2607:f8b0:4864:20::112f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwf5r-0004A9-He for qemu-riscv@nongnu.org; Sat, 28 Oct 2023 04:54:56 -0400 Received: by mail-yw1-x112f.google.com with SMTP id 00721157ae682-5a7dd65052aso24576427b3.0 for ; Sat, 28 Oct 2023 01:54:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698483294; x=1699088094; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4GvjngAwdys+hbv2yWaqY1So3SFMmO3OCd31xaK8qGI=; b=AfDFn8WPw5aIBNAAcZaV+Iaz3YPpH8NdcnWpPZIE4OCB8JhwuPa4jHx8WQkloNGdTF RnShd6cJo16KPpYO/RY9JiRY10V9wy2lwHNCLQuQAGzFp3hyyxtzpKlZJGAstHJ2TaJU 5sSX1wEgGvr5yOAAPHdF6vsCy4EjbyqOkrxey5t7yC8z3iES/Ysts1HygcC4G29woSnO tEDiu6gwqN5t3a9OcYHnlX7X4JmHs7mOSYLd3Gdh8/Cxtb8QXzvIufzwj571IATJg1co 3y08Ew253I+tlS1GMHABeY5ERXSQFcqBl3obtF8P99XNIxQpFBOtkiq2BhfFl7UmKJxa K/fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698483294; x=1699088094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4GvjngAwdys+hbv2yWaqY1So3SFMmO3OCd31xaK8qGI=; b=hqqVh88yJf5uA+lGQLNnO1SH+t0AimvFT6vtR4Es92UmkHoj4MCw07meNIwxz/GSfT ZWR2b5ksQdKmwiUPA/1B6q19cGlTVi/4dGv87ZkOFQN4zYuvrkrZjokpTrwk4lgA84+A fuhhUUyoLh35UiykoRs2NtPJAmozMcHWoitwiShpjBdAJDygS0ZbeZ8Oa4olZu76Fmck n5/yl8F1ELgp2UkDfohj5U/vA+y+tUo35IlZoHBBw4CBNcr+d8ayTxFMqGRpSsaUdvxe eDS0brN4aflPY3OTjr1m7Qn1udDr4o4c3A3DOAuWkBZ9k4asd5wZXlkQAjtpbsNP4LFm IVsA== X-Gm-Message-State: AOJu0Yx67Rr0cXvW0MemqINfTNJjguODihDLEHXrVSR2snDwAkQITWIF U2WOlv9vOcMDJieznAKwa5mUgQ== X-Google-Smtp-Source: AGHT+IFrwgWp9MqxuDteurTY+VPAmxIyuDYnmFoMp1n+MYD8qhr3IojeWp1j+ER4AUMcsrso2t0QNA== X-Received: by 2002:a81:e70b:0:b0:5a1:db6a:6459 with SMTP id x11-20020a81e70b000000b005a1db6a6459mr4650638ywl.40.1698483294669; Sat, 28 Oct 2023 01:54:54 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([191.255.2.33]) by smtp.gmail.com with ESMTPSA id t15-20020a81830f000000b00594fff48796sm1604325ywf.75.2023.10.28.01.54.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Oct 2023 01:54:54 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v6 07/12] target/riscv/tcg: add MISA user options hash Date: Sat, 28 Oct 2023 05:54:22 -0300 Message-ID: <20231028085427.707060-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231028085427.707060-1-dbarboza@ventanamicro.com> References: <20231028085427.707060-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::112f; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x112f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne need to check for user choice for MISA extensions, so let's add the corresponding hash now. It works like the existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits options in the cpu_set_misa_ext_cfg() callback. Note that we can't re-use the same hash from multi-letter extensions because that hash uses cpu->cfg offsets as keys, while for MISA extensions we're using MISA bits as keys. After adding the user hash in cpu_set_misa_ext_cfg(), setting default values with object_property_set_bool() in add_misa_properties() will end up marking the user choice hash with them. Set the default value manually to avoid it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5fdec8f04e..e98953aabf 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -34,6 +34,7 @@ /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; +static GHashTable *misa_ext_user_opts; static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { @@ -695,6 +696,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, return; } + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit), + (gpointer)value); + prev_val = env->misa_ext & misa_bit; if (value == prev_val) { @@ -758,6 +763,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { + CPURISCVState *env = &RISCV_CPU(cpu_obj)->env; bool use_def_vals = riscv_cpu_is_generic(cpu_obj); int i; @@ -778,7 +784,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); + if (misa_cfg->enabled) { + env->misa_ext |= bit; + env->misa_ext_mask |= bit; + } else { + env->misa_ext &= ~bit; + env->misa_ext_mask &= ~bit; + } } } } @@ -1019,6 +1031,7 @@ static void tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu = RISCV_CPU(cs); Object *obj = OBJECT(cpu); + misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); -- 2.41.0