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Tsirkin" To: Sunil V L Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Peter Maydell , Shannon Zhao , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Gerd Hoffmann , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anup Patel , Atish Kumar Patra , Haibo Xu Subject: Re: [PATCH v5 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Message-ID: <20231030101332-mutt-send-email-mst@kernel.org> References: <20231030132058.763556-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: <20231030132058.763556-1-sunilvl@ventanamicro.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.483, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Mon, Oct 30, 2023 at 06:50:45PM +0530, Sunil V L wrote: > This series primarily enables external interrupt controllers (AIA and PLIC) > in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and > MMU related information. > > Below ECRs for these changes are approved by ASWG and will be > available in next ACPI spec release. pci, acpi things look ok Acked-by: Michael S. Tsirkin > 1) MADT (AIA) - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing > 2) RHCT - https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view?usp=sharing > > First two patches in this series are to migrate a couple of functions from > ARM architecture to common code so that RISC-V doesn't need to duplicate > the same. > > The patch set is based on Alistair's riscv-to-apply.next branch. > > These changes are also available in riscv_acpi_b2_v5 branch at: > https://github.com/vlsunil/qemu/ > > Changes since v4: > 1) Updated copyright for new files as per SPDX format suggested by Drew. > 2) Updated RINTC patch to avoid code duplication as suggested by Drew. > 3) Moved mmu offset below cmo in MMU patch as suggested by Drew. > 4) Updated tags. > > Changes since v3: > 1) Addressed comments from Daniel and Drew. > 2) Added a new patch in microvm to use common function for virtio in DSDT. > 3) Rebased to latest riscv-to-apply.next branch and added tags. > > Changes since v2: > 1) Rebased to latest riscv-to-apply.next branch which needed > changing ext_icboz to ext_zicboz in CMO patch. > 2) Fixed node type in MMU node. > 3) Added latest tags. > > Changes since v1: > 1) As per Igor's suggestion, migrated fw_cfg and virtio creation > functions to device specific file instead of generic aml-build.c. > Since ACPI is optional, new files are created and enabled for > build only when CONFIG_ACPI is enabled. > 2) As per Igor's suggestion, properties are added to the GPEX PCI > host to indicate MMIO ranges. The platform fw can initialize > these to appropriate values and the DSDT generator can fetch > the information from the host bus itself. This makes the code > generic instead of machine specific. > 3) Added PLIC patch from Haibo. > 4) Rebased to latest riscv-to-apply.next and added RB tags as > appropriate. > > Sunil V L (13): > hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location > hw/arm/virt-acpi-build.c: Migrate virtio creation to common location > hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT > hw/riscv: virt: Make few IMSIC macros and functions public > hw/riscv/virt-acpi-build.c: Add AIA support in RINTC > hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT > hw/riscv/virt-acpi-build.c: Add APLIC in the MADT > hw/riscv/virt-acpi-build.c: Add CMO information in RHCT > hw/riscv/virt-acpi-build.c: Add MMU node in RHCT > hw/pci-host/gpex: Define properties for MMIO ranges > hw/riscv/virt: Update GPEX MMIO related properties > hw/riscv/virt-acpi-build.c: Add IO controllers and devices > hw/riscv/virt-acpi-build.c: Add PLIC in MADT > > hw/arm/virt-acpi-build.c | 51 +---- > hw/i386/acpi-microvm.c | 15 +- > hw/nvram/fw_cfg-acpi.c | 23 +++ > hw/nvram/meson.build | 1 + > hw/pci-host/gpex-acpi.c | 13 ++ > hw/pci-host/gpex.c | 12 ++ > hw/riscv/Kconfig | 1 + > hw/riscv/virt-acpi-build.c | 323 +++++++++++++++++++++++++++++--- > hw/riscv/virt.c | 72 ++++--- > hw/virtio/meson.build | 1 + > hw/virtio/virtio-acpi.c | 32 ++++ > include/hw/nvram/fw_cfg_acpi.h | 15 ++ > include/hw/pci-host/gpex.h | 28 ++- > include/hw/riscv/virt.h | 26 +++ > include/hw/virtio/virtio-acpi.h | 16 ++ > 15 files changed, 498 insertions(+), 131 deletions(-) > create mode 100644 hw/nvram/fw_cfg-acpi.c > create mode 100644 hw/virtio/virtio-acpi.c > create mode 100644 include/hw/nvram/fw_cfg_acpi.h > create mode 100644 include/hw/virtio/virtio-acpi.h > > -- > 2.39.2