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From: Sunil V L <sunilvl@ventanamicro.com>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Shannon Zhao" <shannon.zhaosl@gmail.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	"Igor Mammedov" <imammedo@redhat.com>,
	"Ani Sinha" <anisinha@redhat.com>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Gerd Hoffmann" <kraxel@redhat.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Weiwei Li" <liweiwei@iscas.ac.cn>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Haibo Xu" <haibo1.xu@intel.com>,
	"Sunil V L" <sunilvl@ventanamicro.com>,
	"Andrew Jones" <ajones@ventanamicro.com>
Subject: [PATCH v5 09/13] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
Date: Mon, 30 Oct 2023 18:50:54 +0530	[thread overview]
Message-ID: <20231030132058.763556-10-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20231030132058.763556-1-sunilvl@ventanamicro.com>

MMU type information is available via MMU node in RHCT. Add this node in
RHCT.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 hw/riscv/virt-acpi-build.c | 36 +++++++++++++++++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 506d487ede..86c38f7c2b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -152,6 +152,8 @@ static void build_rhct(GArray *table_data,
     size_t len, aligned_len;
     uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
     RISCVCPU *cpu = &s->soc[0].harts[0];
+    uint32_t mmu_offset = 0;
+    uint8_t satp_mode_max;
     char *isa;
 
     AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -171,6 +173,10 @@ static void build_rhct(GArray *table_data,
         num_rhct_nodes++;
     }
 
+    if (cpu->cfg.satp_mode.supported != 0) {
+        num_rhct_nodes++;
+    }
+
     /* Number of RHCT nodes*/
     build_append_int_noprefix(table_data, num_rhct_nodes, 4);
 
@@ -226,6 +232,26 @@ static void build_rhct(GArray *table_data,
         }
     }
 
+    /* MMU node structure */
+    if (cpu->cfg.satp_mode.supported != 0) {
+        satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+        mmu_offset = table_data->len - table.table_offset;
+        build_append_int_noprefix(table_data, 2, 2);    /* Type */
+        build_append_int_noprefix(table_data, 8, 2);    /* Length */
+        build_append_int_noprefix(table_data, 0x1, 2);  /* Revision */
+        build_append_int_noprefix(table_data, 0, 1);    /* Reserved */
+        /* MMU Type */
+        if (satp_mode_max == VM_1_10_SV57) {
+            build_append_int_noprefix(table_data, 2, 1);    /* Sv57 */
+        } else if (satp_mode_max == VM_1_10_SV48) {
+            build_append_int_noprefix(table_data, 1, 1);    /* Sv48 */
+        } else if (satp_mode_max == VM_1_10_SV39) {
+            build_append_int_noprefix(table_data, 0, 1);    /* Sv39 */
+        } else {
+            assert(1);
+        }
+    }
+
     /* Hart Info Node */
     for (int i = 0; i < arch_ids->len; i++) {
         len = 16;
@@ -238,17 +264,25 @@ static void build_rhct(GArray *table_data,
             num_offsets++;
         }
 
+        if (mmu_offset) {
+            len += 4;
+            num_offsets++;
+        }
+
         build_append_int_noprefix(table_data, len, 2);
         build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
         /* Number of offsets */
         build_append_int_noprefix(table_data, num_offsets, 2);
         build_append_int_noprefix(table_data, i, 4);   /* ACPI Processor UID */
-
         /* Offsets */
         build_append_int_noprefix(table_data, isa_offset, 4);
         if (cmo_offset) {
             build_append_int_noprefix(table_data, cmo_offset, 4);
         }
+
+        if (mmu_offset) {
+            build_append_int_noprefix(table_data, mmu_offset, 4);
+        }
     }
 
     acpi_table_end(linker, &table);
-- 
2.39.2



  parent reply	other threads:[~2023-10-30 13:23 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-30 13:20 [PATCH v5 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
2023-10-30 13:20 ` [PATCH v5 01/13] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Sunil V L
2023-10-30 13:20 ` [PATCH v5 02/13] hw/arm/virt-acpi-build.c: Migrate virtio " Sunil V L
2023-11-02 12:10   ` Daniel Henrique Barboza
2023-11-02 12:56     ` Sunil V L
2023-10-30 13:20 ` [PATCH v5 03/13] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT Sunil V L
2023-10-30 13:20 ` [PATCH v5 04/13] hw/riscv: virt: Make few IMSIC macros and functions public Sunil V L
2023-10-30 13:20 ` [PATCH v5 05/13] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Sunil V L
2023-10-30 13:20 ` [PATCH v5 06/13] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Sunil V L
2023-10-30 13:20 ` [PATCH v5 07/13] hw/riscv/virt-acpi-build.c: Add APLIC " Sunil V L
2023-10-30 13:20 ` [PATCH v5 08/13] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Sunil V L
2023-10-30 13:20 ` Sunil V L [this message]
2023-11-02  1:00   ` [PATCH v5 09/13] hw/riscv/virt-acpi-build.c: Add MMU node " Alistair Francis
2023-10-30 13:20 ` [PATCH v5 10/13] hw/pci-host/gpex: Define properties for MMIO ranges Sunil V L
2023-10-30 13:39   ` Daniel Henrique Barboza
2023-10-30 13:20 ` [PATCH v5 11/13] hw/riscv/virt: Update GPEX MMIO related properties Sunil V L
2023-10-30 13:20 ` [PATCH v5 12/13] hw/riscv/virt-acpi-build.c: Add IO controllers and devices Sunil V L
2023-10-30 13:20 ` [PATCH v5 13/13] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Sunil V L
2023-10-30 14:13 ` [PATCH v5 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Michael S. Tsirkin
2023-11-02  1:37 ` Alistair Francis

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