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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id p14-20020adfcc8e000000b0032dbf32bd56sm3688282wrj.37.2023.11.01.02.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 02:19:49 -0700 (PDT) Date: Wed, 1 Nov 2023 10:19:48 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v7 01/16] target/riscv: create TYPE_RISCV_VENDOR_CPU Message-ID: <20231101-2b306f5b57863cf8136f568a@orel> References: <20231031203916.197332-1-dbarboza@ventanamicro.com> <20231031203916.197332-2-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231031203916.197332-2-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=ajones@ventanamicro.com; helo=mail-lj1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Tue, Oct 31, 2023 at 05:39:01PM -0300, Daniel Henrique Barboza wrote: > We want to add a new CPU type for bare CPUs that will inherit specific > traits of the 2 existing types: > > - it will allow for extensions to be enabled/disabled, like generic > CPUs; > > - it will NOT inherit defaults, like vendor CPUs. > > We can make this conditions met by adding an explicit type for the > existing vendor CPUs and change the existing logic to not imply that > "not generic" means vendor CPUs. > > Let's add the "vendor" CPU type first. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 30 +++++++++++++++++++++--------- > 2 files changed, 22 insertions(+), 9 deletions(-) > Reviewed-by: Andrew Jones