From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
ajones@ventanamicro.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v8 01/19] target/riscv: create TYPE_RISCV_VENDOR_CPU
Date: Wed, 1 Nov 2023 17:41:46 -0300 [thread overview]
Message-ID: <20231101204204.345470-2-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com>
We want to add a new CPU type for bare CPUs that will inherit specific
traits of the 2 existing types:
- it will allow for extensions to be enabled/disabled, like generic
CPUs;
- it will NOT inherit defaults, like vendor CPUs.
We can make this conditions met by adding an explicit type for the
existing vendor CPUs and change the existing logic to not imply that
"not generic" means vendor CPUs.
Let's add the "vendor" CPU type first.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 30 +++++++++++++++++++++---------
2 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index f3fbe37a2c..7831e86d37 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -24,6 +24,7 @@
#define TYPE_RISCV_CPU "riscv-cpu"
#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
+#define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f40da4c661..822970345c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1725,6 +1725,13 @@ void riscv_cpu_list(void)
.instance_init = initfn \
}
+#define DEFINE_VENDOR_CPU(type_name, initfn) \
+ { \
+ .name = type_name, \
+ .parent = TYPE_RISCV_VENDOR_CPU, \
+ .instance_init = initfn \
+ }
+
static const TypeInfo riscv_cpu_type_infos[] = {
{
.name = TYPE_RISCV_CPU,
@@ -1742,21 +1749,26 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.parent = TYPE_RISCV_CPU,
.abstract = true,
},
+ {
+ .name = TYPE_RISCV_VENDOR_CPU,
+ .parent = TYPE_RISCV_CPU,
+ .abstract = true,
+ },
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
#endif
};
--
2.41.0
next prev parent reply other threads:[~2023-11-01 20:46 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-01 20:41 [PATCH v8 00/19] rv64i CPU, RVA22U64 profile support Daniel Henrique Barboza
2023-11-01 20:41 ` Daniel Henrique Barboza [this message]
2023-11-02 2:32 ` [PATCH v8 01/19] target/riscv: create TYPE_RISCV_VENDOR_CPU Alistair Francis
2023-11-01 20:41 ` [PATCH v8 02/19] target/riscv/tcg: do not use "!generic" CPU checks Daniel Henrique Barboza
2023-11-02 2:38 ` Alistair Francis
2023-11-01 20:41 ` [PATCH v8 03/19] target/riscv/cpu.c: set satp_max_supported in cpu_riscv_set_satp() Daniel Henrique Barboza
2023-11-02 9:24 ` Andrew Jones
2023-11-02 12:53 ` Daniel Henrique Barboza
2023-11-02 13:11 ` Andrew Jones
2023-11-01 20:41 ` [PATCH v8 04/19] target/riscv/cpu.c: set satp_mode_max MBARE during satp_finalize() Daniel Henrique Barboza
2023-11-02 9:32 ` Andrew Jones
2023-11-01 20:41 ` [PATCH v8 05/19] target/riscv/tcg: update priv_ver on user_set extensions Daniel Henrique Barboza
2023-11-02 9:47 ` Andrew Jones
2023-11-02 13:42 ` Daniel Henrique Barboza
2023-11-02 13:48 ` Andrew Jones
2023-11-01 20:41 ` [PATCH v8 06/19] target/riscv: add rv64i CPU Daniel Henrique Barboza
2023-11-02 9:59 ` Andrew Jones
2023-11-02 14:23 ` Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 07/19] target/riscv: add zicbop extension flag Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 08/19] target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 09/19] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 10/19] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 11/19] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 12/19] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 13/19] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-11-01 20:41 ` [PATCH v8 14/19] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-11-01 20:42 ` [PATCH v8 15/19] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-11-01 20:42 ` [PATCH v8 16/19] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-11-01 20:42 ` [PATCH v8 17/19] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-11-01 20:42 ` [PATCH v8 18/19] target/riscv/tcg: validate profiles during finalize Daniel Henrique Barboza
2023-11-01 20:42 ` [PATCH v8 19/19] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Daniel Henrique Barboza
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