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Tsirkin" To: Sunil V L Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Peter Maydell , Shannon Zhao , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Gerd Hoffmann , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anup Patel , Atish Kumar Patra , Haibo Xu Subject: Re: [PATCH v7 10/13] hw/pci-host/gpex: Define properties for MMIO ranges Message-ID: <20231106123605-mutt-send-email-mst@kernel.org> References: <20231103031649.2769834-1-sunilvl@ventanamicro.com> <20231103031649.2769834-11-sunilvl@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: <20231103031649.2769834-11-sunilvl@ventanamicro.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Fri, Nov 03, 2023 at 08:46:46AM +0530, Sunil V L wrote: > ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit > and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of > making these values machine specific, create properties for the GPEX > host bridge with default value 0. During initialization, the firmware > can initialize these properties with correct values for the platform. > This basically allows DSDT generator code independent of the machine > specific memory map accesses. > > Suggested-by: Igor Mammedov > Signed-off-by: Sunil V L > Acked-by: Alistair Francis > Acked-by: Michael S. Tsirkin > Reviewed-by: Daniel Henrique Barboza > --- > hw/pci-host/gpex-acpi.c | 13 +++++++++++++ > hw/pci-host/gpex.c | 12 ++++++++++++ > include/hw/pci-host/gpex.h | 28 ++++++++++++++++++++-------- > 3 files changed, 45 insertions(+), 8 deletions(-) > > diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c > index 1092dc3b70..f69413ea2c 100644 > --- a/hw/pci-host/gpex-acpi.c > +++ b/hw/pci-host/gpex-acpi.c > @@ -281,3 +281,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) > > crs_range_set_free(&crs_range_set); > } > + > +void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq) > +{ > + bool ambig; > + Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, &ambig); > + > + if (!obj || ambig) { > + return; > + } > + > + GPEX_HOST(obj)->gpex_cfg.irq = irq; > + acpi_dsdt_add_gpex(scope, &GPEX_HOST(obj)->gpex_cfg); > +} > diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c > index a6752fac5e..41f4e73f6e 100644 > --- a/hw/pci-host/gpex.c > +++ b/hw/pci-host/gpex.c > @@ -154,6 +154,18 @@ static Property gpex_host_properties[] = { > */ > DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost, > allow_unmapped_accesses, true), > + DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0), > + DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0), > + DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0), > + DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0), > + DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost, > + gpex_cfg.mmio32.base, 0), > + DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost, > + gpex_cfg.mmio32.size, 0), > + DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost, > + gpex_cfg.mmio64.base, 0), > + DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost, > + gpex_cfg.mmio64.size, 0), > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h > index b0240bd768..441c6b8b20 100644 > --- a/include/hw/pci-host/gpex.h > +++ b/include/hw/pci-host/gpex.h > @@ -40,6 +40,15 @@ struct GPEXRootState { > /*< public >*/ > }; > > +struct GPEXConfig { > + MemMapEntry ecam; > + MemMapEntry mmio32; > + MemMapEntry mmio64; > + MemMapEntry pio; > + int irq; > + PCIBus *bus; > +}; > + > struct GPEXHost { > /*< private >*/ > PCIExpressHost parent_obj; > @@ -55,19 +64,22 @@ struct GPEXHost { > int irq_num[GPEX_NUM_IRQS]; > > bool allow_unmapped_accesses; > -}; > > -struct GPEXConfig { > - MemMapEntry ecam; > - MemMapEntry mmio32; > - MemMapEntry mmio64; > - MemMapEntry pio; > - int irq; > - PCIBus *bus; > + struct GPEXConfig gpex_cfg; > }; > > int gpex_set_irq_num(GPEXHost *s, int index, int gsi); > > void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg); > +void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq); > + > +#define PCI_HOST_PIO_BASE "pio-base" > +#define PCI_HOST_PIO_SIZE "pio-size" > +#define PCI_HOST_ECAM_BASE "ecam-base" > +#define PCI_HOST_ECAM_SIZE "ecam-size" > +#define PCI_HOST_BELOW_4G_MMIO_BASE "below-4g-mmio-base" > +#define PCI_HOST_BELOW_4G_MMIO_SIZE "below-4g-mmio-size" > +#define PCI_HOST_ABOVE_4G_MMIO_BASE "above-4g-mmio-base" > +#define PCI_HOST_ABOVE_4G_MMIO_SIZE "above-4g-mmio-size" If there's no reason to allow users to tweak these directly then I think we should prefix these with "x-" so users know we don't commit to these as a stable API. Right? > #endif /* HW_GPEX_H */ > -- > 2.39.2