From: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Jie Luo <quic_luoj@quicinc.com>
Cc: <andrew@lunn.ch>, <hkallweit1@gmail.com>, <linux@armlinux.org.uk>,
<davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
<pabeni@redhat.com>, <netdev@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/3] net: phy: at803x: add QCA8084 ethernet phy support
Date: Fri, 10 Nov 2023 10:18:41 +0100 [thread overview]
Message-ID: <20231110101841.27aba547@fedora> (raw)
In-Reply-To: <0898312d-4796-c142-6401-c9d802d19ff4@quicinc.com>
On Fri, 10 Nov 2023 16:53:39 +0800
Jie Luo <quic_luoj@quicinc.com> wrote:
> On 11/9/2023 5:16 PM, Maxime Chevallier wrote:
> > Hello,
> >
> > On Thu, 9 Nov 2023 16:32:36 +0800
> > Jie Luo <quic_luoj@quicinc.com> wrote:
> >
> > [...]
> >
> >>> What I understand from this is that this PHY can be used either as a
> >>> switch, in which case port 4 would be connected to the host interface
> >>> at up to 2.5G, or as a quad-phy, but since it uses QUSGMII the link
> >>> speed would be limited to 1G per-port, is that correct ?
> >>
> >> When the PHY works on the interface mode QUSGMII for quad-phy, all 4
> >> PHYs can support to the max link speed 2.5G, actually the PHY can
> >> support to max link speed 2.5G for all supported interface modes
> >> including qusgmii and sgmii.
> >
> > I'm a bit confused then, as the USGMII spec says that Quad USGMII really
> > is for quad 10/100/1000 speeds, using 10b/8b encoding.
> >
> > Aren't you using the USXGMII mode instead, which can convey 4 x 2.5Gbps
> > with 66b/64b encoding ?
> >
> > Thanks,
> >
> > Maxime
>
> Hi Maxime,
> Yes, for quad PHY mode, it is using 66b/64 encoding.
>
> it seems that PHY_INTERFACE_MODE_USXGMII is for single port,
> so i take the interface name PHY_INTERFACE_MODE_QUSGMII for
> quad PHYs here.
I see, when I added the QUSGMII mode I wrongly stated that it came from
the USXGMII spec where it really comes from USGMII, my bad.
> can we apply PHY_INTERFACE_MODE_USXGMII to quad PHYs in this
> case(qca8084 quad PHY mode)?
From what I can see, the USXGMII mode in the kernel is used as the
single-port 10G mode of usxgmii. You might need to create a new mode
for quad usxgmii at 10G, the spec calls it 10G-QXGMII I think, but as
the spec defines quite a lot of modes, should we define all of them or
rely on some other parameters to select the actual mode ?
Andrew, Heiner, Russell, what do you think ?
Maxime
> Thanks,
> Jie.
next prev parent reply other threads:[~2023-11-10 17:56 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-08 11:34 [PATCH v2 0/3] add qca8084 ethernet phy driver Luo Jie
2023-11-08 11:34 ` [PATCH v2 1/3] net: phy: at803x: add QCA8084 ethernet phy support Luo Jie
2023-11-08 12:12 ` Maxime Chevallier
2023-11-09 8:32 ` Jie Luo
2023-11-09 9:16 ` Maxime Chevallier
2023-11-10 8:53 ` Jie Luo
2023-11-10 9:17 ` Jie Luo
2023-11-10 9:33 ` Maxime Chevallier
2023-11-10 9:56 ` Jie Luo
2023-11-11 22:54 ` Vladimir Oltean
2023-11-12 11:27 ` Jie Luo
2023-11-12 23:58 ` Vladimir Oltean
2023-11-13 12:42 ` Jie Luo
2023-11-13 13:42 ` Russell King (Oracle)
2023-11-13 19:51 ` Vladimir Oltean
2024-01-02 14:37 ` Russell King (Oracle)
2024-01-03 13:25 ` Jie Luo
2023-11-10 9:18 ` Maxime Chevallier [this message]
2023-11-13 15:11 ` Russell King (Oracle)
2023-11-14 14:09 ` Jie Luo
2023-11-08 11:34 ` [PATCH v2 2/3] net: phy: at803x: Add qca8084_config_init function Luo Jie
2023-11-08 11:34 ` [PATCH v2 3/3] net: phy: qca8084: add qca8084_link_change_notify Luo Jie
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