From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39BA623DF for ; Sun, 12 Nov 2023 04:12:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WIBjrF21" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699762333; x=1731298333; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KgNwZKlEknUh48ho6jIqFjsi+lR3uCezgczS6gTj3Dk=; b=WIBjrF219XP6zrvOyHqPgz8Clp2DHwy7fS2xRX2F8FUwdz3IVw5mj7DG vOyjUSy+m1Jorq4+46ap7Njjpshh1r8JcWdyWRkmwlZRnpTA/WYWWGtnc /2KIgSxTLWWE0Oazpyf+UbJmIymd+chN/xCA8aQgwwHc8eRmBaluX/Acz XU5TbHdw5Q92Z9Ny4ga1zWUf2pMtaSOXzgqOV/JAufZ5lNgekaBEDUqzn sUt7wFg/+8Q27XRadX00xZMEhkQmyidYgXbdcO7uDcCIIj4D42B7MNMMC Qlh5ppvcZyNPrH0PSc+c8dYkpeiiAY5Jil6pDliY1luwO/gcHwEyonO/h A==; X-IronPort-AV: E=McAfee;i="6600,9927,10891"; a="476533895" X-IronPort-AV: E=Sophos;i="6.03,296,1694761200"; d="scan'208";a="476533895" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2023 20:12:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10891"; a="713936754" X-IronPort-AV: E=Sophos;i="6.03,296,1694761200"; d="scan'208";a="713936754" Received: from srinivas-otcpl-7600.jf.intel.com (HELO jacob-builder.jf.intel.com) ([10.54.39.116]) by orsmga003.jf.intel.com with ESMTP; 11 Nov 2023 20:12:08 -0800 From: Jacob Pan To: LKML , X86 Kernel , iommu@lists.linux.dev, Thomas Gleixner , "Lu Baolu" , kvm@vger.kernel.org, Dave Hansen , Joerg Roedel , "H. Peter Anvin" , "Borislav Petkov" , "Ingo Molnar" Cc: Raj Ashok , "Tian, Kevin" , maz@kernel.org, peterz@infradead.org, seanjc@google.com, "Robin Murphy" , Jacob Pan Subject: [PATCH RFC 06/13] x86/irq: Unionize PID.PIR for 64bit access w/o casting Date: Sat, 11 Nov 2023 20:16:36 -0800 Message-Id: <20231112041643.2868316-7-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231112041643.2868316-1-jacob.jun.pan@linux.intel.com> References: <20231112041643.2868316-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Make PIR field into u64 such that atomic xchg64 can be used without ugly casting. Suggested-by: Thomas Gleixner Signed-off-by: Jacob Pan --- arch/x86/include/asm/posted_intr.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/posted_intr.h b/arch/x86/include/asm/posted_intr.h index 2cd9ac1af835..3af00f5395e4 100644 --- a/arch/x86/include/asm/posted_intr.h +++ b/arch/x86/include/asm/posted_intr.h @@ -9,7 +9,10 @@ /* Posted-Interrupt Descriptor */ struct pi_desc { - u32 pir[8]; /* Posted interrupt requested */ + union { + u32 pir[8]; /* Posted interrupt requested */ + u64 pir_l[4]; + }; union { struct { /* bit 256 - Outstanding Notification */ -- 2.25.1