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From: Jisheng Zhang <jszhang@kernel.org>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Chao Wei <chao.wei@sophgo.com>,
	Chen Wang <unicorn_wang@outlook.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: [PATCH 1/2] riscv: dts: cv1800b: add pinctrl node for cv1800b
Date: Mon, 13 Nov 2023 08:57:01 +0800	[thread overview]
Message-ID: <20231113005702.2467-2-jszhang@kernel.org> (raw)
In-Reply-To: <20231113005702.2467-1-jszhang@kernel.org>

Add the reset device tree node to cv1800b SoC reusing the
pinctrl-single driver.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h

diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
new file mode 100644
index 000000000000..ed78b6fb3142
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
+ *
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
+#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
+
+#define MUX_M0		0
+#define MUX_M1		1
+#define MUX_M2		2
+#define MUX_M3		3
+#define MUX_M4		4
+#define MUX_M5		5
+#define MUX_M6		6
+#define MUX_M7		7
+
+#endif
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index e04df04a91c0..7a44d8e8672b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -6,6 +6,8 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/reset/sophgo,cv1800b-reset.h>
 
+#include "cv-pinctrl.h"
+
 / {
 	compatible = "sophgo,cv1800b";
 	#address-cells = <1>;
@@ -55,6 +57,14 @@ soc {
 		dma-noncoherent;
 		ranges;
 
+		pinctrl0: pinctrl@3001000 {
+			compatible = "pinctrl-single";
+			reg = <0x3001000 0x130>;
+			#pinctrl-cells = <1>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x00000007>;
+		};
+
 		rst: reset-controller@3003000 {
 			compatible = "sophgo,cv1800b-reset";
 			reg = <0x03003000 0x1000>;
-- 
2.42.0


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WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Chao Wei <chao.wei@sophgo.com>,
	Chen Wang <unicorn_wang@outlook.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: [PATCH 1/2] riscv: dts: cv1800b: add pinctrl node for cv1800b
Date: Mon, 13 Nov 2023 08:57:01 +0800	[thread overview]
Message-ID: <20231113005702.2467-2-jszhang@kernel.org> (raw)
In-Reply-To: <20231113005702.2467-1-jszhang@kernel.org>

Add the reset device tree node to cv1800b SoC reusing the
pinctrl-single driver.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h

diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
new file mode 100644
index 000000000000..ed78b6fb3142
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
+ *
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
+#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
+
+#define MUX_M0		0
+#define MUX_M1		1
+#define MUX_M2		2
+#define MUX_M3		3
+#define MUX_M4		4
+#define MUX_M5		5
+#define MUX_M6		6
+#define MUX_M7		7
+
+#endif
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index e04df04a91c0..7a44d8e8672b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -6,6 +6,8 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/reset/sophgo,cv1800b-reset.h>
 
+#include "cv-pinctrl.h"
+
 / {
 	compatible = "sophgo,cv1800b";
 	#address-cells = <1>;
@@ -55,6 +57,14 @@ soc {
 		dma-noncoherent;
 		ranges;
 
+		pinctrl0: pinctrl@3001000 {
+			compatible = "pinctrl-single";
+			reg = <0x3001000 0x130>;
+			#pinctrl-cells = <1>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x00000007>;
+		};
+
 		rst: reset-controller@3003000 {
 			compatible = "sophgo,cv1800b-reset";
 			reg = <0x03003000 0x1000>;
-- 
2.42.0


  reply	other threads:[~2023-11-13  1:09 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-13  0:57 [PATCH 0/2] riscv: sophgo: add pinctrl support for cv1800b Jisheng Zhang
2023-11-13  0:57 ` Jisheng Zhang
2023-11-13  0:57 ` Jisheng Zhang [this message]
2023-11-13  0:57   ` [PATCH 1/2] riscv: dts: cv1800b: add pinctrl node " Jisheng Zhang
2023-11-13  1:51   ` Samuel Holland
2023-11-13  1:51     ` Samuel Holland
2023-11-13 13:03     ` Jisheng Zhang
2023-11-13 13:03       ` Jisheng Zhang
2023-11-13 13:29       ` Conor Dooley
2023-11-13 13:29         ` Conor Dooley
2023-11-13 13:49         ` Samuel Holland
2023-11-13 13:49           ` Samuel Holland
2023-11-14  1:38   ` Chen Wang
2023-11-14  1:38     ` Chen Wang
2023-11-14 14:46     ` Jisheng Zhang
2023-11-14 14:46       ` Jisheng Zhang
2023-11-14  2:07   ` Chen Wang
2023-11-14  2:07     ` Chen Wang
2023-11-16 16:36   ` Rob Herring
2023-11-16 16:36     ` Rob Herring
2023-11-13  0:57 ` [PATCH 2/2] riscv: dts: sophgo: set pinctrl for uart0 Jisheng Zhang
2023-11-13  0:57   ` Jisheng Zhang
2024-01-17  9:03 ` [PATCH 0/2] riscv: sophgo: add pinctrl support for cv1800b Chen Wang
2024-01-17  9:03   ` Chen Wang
2024-01-18  1:23   ` Jisheng Zhang
2024-01-18  1:23     ` Jisheng Zhang
2024-06-12  5:02 ` Inochi Amaoto
2024-06-12  5:02   ` Inochi Amaoto

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