From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 334E31FDE; Fri, 1 Dec 2023 03:28:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p7HtC0TO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B46F2C433C9; Fri, 1 Dec 2023 03:28:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701401325; bh=dprFJ6x5ESRUrN+ixh3IhUPlCeLLde0KvclcLHkX+mo=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=p7HtC0TO+dp4tn5bU5Hi4lZpVik3hHJfF0fkgiRsWE2kUdwMXbMgvb607D/fTgQIC 0XBNl4jDkkm5f+yscuk3rbecTDtXuOpsOrdjtHX4nxweXdkV2O8rrNeDj9olRlcChW FmLe19I0xWDfCSAoHuN6tDppou5I+N7GhIW9rYaGGGYMee7vdFoU3r9aSgCBygwhiY UN6GcazerG4e+jFlGa9WtWh6+6V2s4TP3pN0dks8aBqC4rCystihZ4DUAg6TJkEUQT vDx1pC8KFN3jmHpMGJYfZBEvyD+61N3cQNsfJQ841lEkI3aqirTPOP5TOjDgB+xxnp IAVW9Qn+f240Q== Date: Fri, 1 Dec 2023 08:58:31 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Manivannan Sadhasivam , bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: Re: [PATCH v4 4/4] PCI: layerscape: Add suspend/resume for ls1043a Message-ID: <20231201032831.GA2898@thinkpad> References: <20231129214412.327633-1-Frank.Li@nxp.com> <20231129214412.327633-5-Frank.Li@nxp.com> <20231130165100.GV3043@thinkpad> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Thu, Nov 30, 2023 at 03:17:39PM -0500, Frank Li wrote: > On Thu, Nov 30, 2023 at 10:21:00PM +0530, Manivannan Sadhasivam wrote: > > On Wed, Nov 29, 2023 at 04:44:12PM -0500, Frank Li wrote: > > > In the suspend path, PME_Turn_Off message is sent to the endpoint to > > > transition the link to L2/L3_Ready state. In this SoC, there is no way to > > > check if the controller has received the PME_To_Ack from the endpoint or > > > not. So to be on the safer side, the driver just waits for > > > PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF > > > bit to complete the PME_Turn_Off handshake. This link would then enter > > > L2/L3 state depending on the VAUX supply. > > > > > > In the resume path, the link is brought back from L2 to L0 by doing a > > > software reset. > > > > > > > Same comment on the patch description as on patch 2/4. > > > > > Signed-off-by: Frank Li > > > --- > > > > > > Notes: > > > Change from v3 to v4 > > > - Call scfg_pcie_send_turnoff_msg() shared with ls1021a > > > - update commit message > > > > > > Change from v2 to v3 > > > - Remove ls_pcie_lut_readl(writel) function > > > > > > Change from v1 to v2 > > > - Update subject 'a' to 'A' > > > > > > drivers/pci/controller/dwc/pci-layerscape.c | 63 ++++++++++++++++++++- > > > 1 file changed, 62 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > > > index 590e07bb27002..d39700b3afaaa 100644 > > > --- a/drivers/pci/controller/dwc/pci-layerscape.c > > > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > > > @@ -41,6 +41,15 @@ > > > #define SCFG_PEXSFTRSTCR 0x190 > > > #define PEXSR(idx) BIT(idx) > > > > > > +/* LS1043A PEX PME control register */ > > > +#define SCFG_PEXPMECR 0x144 > > > +#define PEXPME(idx) BIT(31 - (idx) * 4) > > > + > > > +/* LS1043A PEX LUT debug register */ > > > +#define LS_PCIE_LDBG 0x7fc > > > +#define LDBG_SR BIT(30) > > > +#define LDBG_WE BIT(31) > > > + > > > #define PCIE_IATU_NUM 6 > > > > > > struct ls_pcie_drvdata { > > > @@ -225,6 +234,45 @@ static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) > > > return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); > > > } > > > > > > +static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > > > +{ > > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + struct ls_pcie *pcie = to_ls_pcie(pci); > > > + > > > + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index)); > > > +} > > > + > > > +static int ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp) > > > +{ > > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + struct ls_pcie *pcie = to_ls_pcie(pci); > > > + u32 val; > > > + > > > + /* > > > + * Only way let PEX module exit L2 is do a software reset. > > > > Can you expand PEX? What is it used for? > > > > Also if the reset is only for the PEX module, please use the same comment in > > both patches 2 and 4. Patch 2 doesn't mention PEX in the comment. > > After read spec again, I think PEX is pci express. So it should software > reset controller. I don't know what exactly did in the chip. But without > below code, PCIe can't exit L2/L3. > > Any harmful if dwc controller reset? Anyway these code works well with > intel network card. If it is a DWC controller reset, then we need to program all CSRs like DBI etc... But from your reply it seems like the reset is limited to some module, so it is fine. - Mani > > Frank > > > > > - Mani > > > > > + * LDBG_WE: allows the user to have write access to the PEXDBG[SR] for both setting and > > > + * clearing the soft reset on the PEX module. > > > + * LDBG_SR: When SR is set to 1, the PEX module enters soft reset. > > > + */ > > > + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); > > > + val |= LDBG_WE; > > > + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); > > > + > > > + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); > > > + val |= LDBG_SR; > > > + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); > > > + > > > + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); > > > + val &= ~LDBG_SR; > > > + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); > > > + > > > + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); > > > + val &= ~LDBG_WE; > > > + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); > > > + > > > + return 0; > > > +} > > > + > > > static const struct dw_pcie_host_ops ls_pcie_host_ops = { > > > .host_init = ls_pcie_host_init, > > > .pme_turn_off = ls_pcie_send_turnoff_msg, > > > @@ -242,6 +290,19 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { > > > .exit_from_l2 = ls1021a_pcie_exit_from_l2, > > > }; > > > > > > +static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = { > > > + .host_init = ls_pcie_host_init, > > > + .pme_turn_off = ls1043a_pcie_send_turnoff_msg, > > > +}; > > > + > > > +static const struct ls_pcie_drvdata ls1043a_drvdata = { > > > + .pf_lut_off = 0x10000, > > > + .pm_support = true, > > > + .scfg_support = true, > > > + .ops = &ls1043a_pcie_host_ops, > > > + .exit_from_l2 = ls1043a_pcie_exit_from_l2, > > > +}; > > > + > > > static const struct ls_pcie_drvdata layerscape_drvdata = { > > > .pf_lut_off = 0xc0000, > > > .pm_support = true, > > > @@ -252,7 +313,7 @@ static const struct of_device_id ls_pcie_of_match[] = { > > > { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, > > > { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, > > > { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, > > > - { .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata }, > > > + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, > > > { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, > > > { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, > > > { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, > > > -- > > > 2.34.1 > > > > > > > -- > > மணிவண்ணன் சதாசிவம் -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA701C4167B for ; Fri, 1 Dec 2023 03:29:47 +0000 (UTC) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=p7HtC0TO; dkim-atps=neutral Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4ShJTQ0f5Wz3cVF for ; Fri, 1 Dec 2023 14:29:46 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=p7HtC0TO; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kernel.org (client-ip=2604:1380:4601:e00::1; helo=ams.source.kernel.org; envelope-from=mani@kernel.org; receiver=lists.ozlabs.org) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4ShJSQ2mqxz3c5k for ; Fri, 1 Dec 2023 14:28:54 +1100 (AEDT) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id A1B2CB84612; Fri, 1 Dec 2023 03:28:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B46F2C433C9; Fri, 1 Dec 2023 03:28:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701401325; bh=dprFJ6x5ESRUrN+ixh3IhUPlCeLLde0KvclcLHkX+mo=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=p7HtC0TO+dp4tn5bU5Hi4lZpVik3hHJfF0fkgiRsWE2kUdwMXbMgvb607D/fTgQIC 0XBNl4jDkkm5f+yscuk3rbecTDtXuOpsOrdjtHX4nxweXdkV2O8rrNeDj9olRlcChW FmLe19I0xWDfCSAoHuN6tDppou5I+N7GhIW9rYaGGGYMee7vdFoU3r9aSgCBygwhiY UN6GcazerG4e+jFlGa9WtWh6+6V2s4TP3pN0dks8aBqC4rCystihZ4DUAg6TJkEUQT vDx1pC8KFN3jmHpMGJYfZBEvyD+61N3cQNsfJQ841lEkI3aqirTPOP5TOjDgB+xxnp IAVW9Qn+f240Q== Date: Fri, 1 Dec 2023 08:58:31 +0530 From: Manivannan Sadhasivam To: Frank Li Subject: Re: [PATCH v4 4/4] PCI: layerscape: Add suspend/resume for ls1043a Message-ID: <20231201032831.GA2898@thinkpad> References: <20231129214412.327633-1-Frank.Li@nxp.com> <20231129214412.327633-5-Frank.Li@nxp.com> <20231130165100.GV3043@thinkpad> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: imx@lists.linux.dev, kw@linux.com, linux-pci@vger.kernel.org, lpieralisi@kernel.org, linux-kernel@vger.kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, Manivannan Sadhasivam , bhelgaas@google.com, roy.zang@nxp.com, linuxppc-dev@lists.ozlabs.org, robh@kernel.org, linux-arm-kernel@lists.infradead.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Nov 30, 2023 at 03:17:39PM -0500, Frank Li wrote: > On Thu, Nov 30, 2023 at 10:21:00PM +0530, Manivannan Sadhasivam wrote: > > On Wed, Nov 29, 2023 at 04:44:12PM -0500, Frank Li wrote: > > > In the suspend path, PME_Turn_Off message is sent to the endpoint to > > > transition the link to L2/L3_Ready state. In this SoC, there is no way to > > > check if the controller has received the PME_To_Ack from the endpoint or > > > not. So to be on the safer side, the driver just waits for > > > PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF > > > bit to complete the PME_Turn_Off handshake. This link would then enter > > > L2/L3 state depending on the VAUX supply. > > > > > > In the resume path, the link is brought back from L2 to L0 by doing a > > > software reset. > > > > > > > Same comment on the patch description as on patch 2/4. > > > > > Signed-off-by: Frank Li > > > --- > > > > > > Notes: > > > Change from v3 to v4 > > > - Call scfg_pcie_send_turnoff_msg() shared with ls1021a > > > - update commit message > > > > > > Change from v2 to v3 > > > - Remove ls_pcie_lut_readl(writel) function > > > > > > Change from v1 to v2 > > > - Update subject 'a' to 'A' > > > > > > drivers/pci/controller/dwc/pci-layerscape.c | 63 ++++++++++++++++++++- > > > 1 file changed, 62 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > > > index 590e07bb27002..d39700b3afaaa 100644 > > > --- a/drivers/pci/controller/dwc/pci-layerscape.c > > > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > > > @@ -41,6 +41,15 @@ > > > #define SCFG_PEXSFTRSTCR 0x190 > > > #define PEXSR(idx) BIT(idx) > > > > > > +/* LS1043A PEX PME control register */ > > > +#define SCFG_PEXPMECR 0x144 > > > +#define PEXPME(idx) BIT(31 - (idx) * 4) > > > + > > > +/* LS1043A PEX LUT debug register */ > > > +#define LS_PCIE_LDBG 0x7fc > > > +#define LDBG_SR BIT(30) > > > +#define LDBG_WE BIT(31) > > > + > > > #define PCIE_IATU_NUM 6 > > > > > > struct ls_pcie_drvdata { > > > @@ -225,6 +234,45 @@ static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) > > > return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); > > > } > > > > > > +static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > > > +{ > > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + struct ls_pcie *pcie = to_ls_pcie(pci); > > > + > > > + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index)); > > > +} > > > + > > > +static int ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp) > > > +{ > > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + struct ls_pcie *pcie = to_ls_pcie(pci); > > > + u32 val; > > > + > > > + /* > > > + * Only way let PEX module exit L2 is do a software reset. > > > > Can you expand PEX? What is it used for? > > > > Also if the reset is only for the PEX module, please use the same comment in > > both patches 2 and 4. Patch 2 doesn't mention PEX in the comment. > > After read spec again, I think PEX is pci express. So it should software > reset controller. I don't know what exactly did in the chip. But without > below code, PCIe can't exit L2/L3. > > Any harmful if dwc controller reset? Anyway these code works well with > intel network card. If it is a DWC controller reset, then we need to program all CSRs like DBI etc... But from your reply it seems like the reset is limited to some module, so it is fine. - Mani > > Frank > > > > > - Mani > > > > > + * LDBG_WE: allows the user to have write access to the PEXDBG[SR] for both setting and > > > + * clearing the soft reset on the PEX module. > > > + * LDBG_SR: When SR is set to 1, the PEX module enters soft reset. > > > + */ > > > + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); > > > + val |= LDBG_WE; > > > + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); > > > + > > > + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); > > > + val |= LDBG_SR; > > > + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); > > > + > > > + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); > > > + val &= ~LDBG_SR; > > > + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); > > > + > > > + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); > > > + val &= ~LDBG_WE; > > > + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); > > > + > > > + return 0; > > > +} > > > + > > > static const struct dw_pcie_host_ops ls_pcie_host_ops = { > > > .host_init = ls_pcie_host_init, > > > .pme_turn_off = ls_pcie_send_turnoff_msg, > > > @@ -242,6 +290,19 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { > > > .exit_from_l2 = ls1021a_pcie_exit_from_l2, > > > }; > > > > > > +static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = { > > > + .host_init = ls_pcie_host_init, > > > + .pme_turn_off = ls1043a_pcie_send_turnoff_msg, > > > +}; > > > + > > > +static const struct ls_pcie_drvdata ls1043a_drvdata = { > > > + .pf_lut_off = 0x10000, > > > + .pm_support = true, > > > + .scfg_support = true, > > > + .ops = &ls1043a_pcie_host_ops, > > > + .exit_from_l2 = ls1043a_pcie_exit_from_l2, > > > +}; > > > + > > > static const struct ls_pcie_drvdata layerscape_drvdata = { > > > .pf_lut_off = 0xc0000, > > > .pm_support = true, > > > @@ -252,7 +313,7 @@ static const struct of_device_id ls_pcie_of_match[] = { > > > { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, > > > { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, > > > { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, > > > - { .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata }, > > > + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, > > > { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, > > > { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, > > > { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, > > > -- > > > 2.34.1 > > > > > > > -- > > மணிவண்ணன் சதாசிவம் -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1C7BC4167B for ; Fri, 1 Dec 2023 03:29:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BWWkz8WRI1Bkkxzkwn41EDtM2C/Okd+2tTrqA8eUEYg=; b=XO6CEC4s4c5I5M m06sYxA7FicjQTkJtTBpRcSl85cEXAXtT80nMEvM48J5KzYJtHdZlx6g7fjmuGdAbmHM6eSd1kqd7 qJT0D50ZYg/iaMEBgVTn2F/kjzQFVz0/WPY/zFFfKbOU76D1Zs5JJiWwCFKmbkB7Oua3riWZCbnPy CuhP4kDRC01kyS9uC/em44kq9BI9gVIW36lfZlJYDoso6yDok0l7M4G6NGlyKsYmhD5Jf56gcD9Rc XiM8/FKmRFojhGUMqtpYl+pAixzZx29h3GfqVED14jznkRxnG54ypbwbfhRavCj0gEaDDkuSr98nP vRfbrpWM0EsYyL3Rt9Sg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r8uCw-00CVx7-2H; Fri, 01 Dec 2023 03:28:50 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r8uCt-00CVwM-0U for linux-arm-kernel@lists.infradead.org; Fri, 01 Dec 2023 03:28:48 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id A1B2CB84612; Fri, 1 Dec 2023 03:28:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B46F2C433C9; Fri, 1 Dec 2023 03:28:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701401325; bh=dprFJ6x5ESRUrN+ixh3IhUPlCeLLde0KvclcLHkX+mo=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=p7HtC0TO+dp4tn5bU5Hi4lZpVik3hHJfF0fkgiRsWE2kUdwMXbMgvb607D/fTgQIC 0XBNl4jDkkm5f+yscuk3rbecTDtXuOpsOrdjtHX4nxweXdkV2O8rrNeDj9olRlcChW FmLe19I0xWDfCSAoHuN6tDppou5I+N7GhIW9rYaGGGYMee7vdFoU3r9aSgCBygwhiY UN6GcazerG4e+jFlGa9WtWh6+6V2s4TP3pN0dks8aBqC4rCystihZ4DUAg6TJkEUQT vDx1pC8KFN3jmHpMGJYfZBEvyD+61N3cQNsfJQ841lEkI3aqirTPOP5TOjDgB+xxnp IAVW9Qn+f240Q== Date: Fri, 1 Dec 2023 08:58:31 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Manivannan Sadhasivam , bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: Re: [PATCH v4 4/4] PCI: layerscape: Add suspend/resume for ls1043a Message-ID: <20231201032831.GA2898@thinkpad> References: <20231129214412.327633-1-Frank.Li@nxp.com> <20231129214412.327633-5-Frank.Li@nxp.com> <20231130165100.GV3043@thinkpad> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_192847_468051_4E284C54 X-CRM114-Status: GOOD ( 38.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCBOb3YgMzAsIDIwMjMgYXQgMDM6MTc6MzlQTSAtMDUwMCwgRnJhbmsgTGkgd3JvdGU6 Cj4gT24gVGh1LCBOb3YgMzAsIDIwMjMgYXQgMTA6MjE6MDBQTSArMDUzMCwgTWFuaXZhbm5hbiBT YWRoYXNpdmFtIHdyb3RlOgo+ID4gT24gV2VkLCBOb3YgMjksIDIwMjMgYXQgMDQ6NDQ6MTJQTSAt MDUwMCwgRnJhbmsgTGkgd3JvdGU6Cj4gPiA+IEluIHRoZSBzdXNwZW5kIHBhdGgsIFBNRV9UdXJu X09mZiBtZXNzYWdlIGlzIHNlbnQgdG8gdGhlIGVuZHBvaW50IHRvCj4gPiA+IHRyYW5zaXRpb24g dGhlIGxpbmsgdG8gTDIvTDNfUmVhZHkgc3RhdGUuIEluIHRoaXMgU29DLCB0aGVyZSBpcyBubyB3 YXkgdG8KPiA+ID4gY2hlY2sgaWYgdGhlIGNvbnRyb2xsZXIgaGFzIHJlY2VpdmVkIHRoZSBQTUVf VG9fQWNrIGZyb20gdGhlIGVuZHBvaW50IG9yCj4gPiA+IG5vdC4gU28gdG8gYmUgb24gdGhlIHNh ZmVyIHNpZGUsIHRoZSBkcml2ZXIganVzdCB3YWl0cyBmb3IKPiA+ID4gUENJRV9QTUVfVE9fTDJf VElNRU9VVF9VUyBiZWZvcmUgYXNzZXJ0aW5nIHRoZSBTb0Mgc3BlY2lmaWMgUE1YTVRUVVJOT0ZG Cj4gPiA+IGJpdCB0byBjb21wbGV0ZSB0aGUgUE1FX1R1cm5fT2ZmIGhhbmRzaGFrZS4gVGhpcyBs aW5rIHdvdWxkIHRoZW4gZW50ZXIKPiA+ID4gTDIvTDMgc3RhdGUgZGVwZW5kaW5nIG9uIHRoZSBW QVVYIHN1cHBseS4KPiA+ID4gCj4gPiA+IEluIHRoZSByZXN1bWUgcGF0aCwgdGhlIGxpbmsgaXMg YnJvdWdodCBiYWNrIGZyb20gTDIgdG8gTDAgYnkgZG9pbmcgYQo+ID4gPiBzb2Z0d2FyZSByZXNl dC4KPiA+ID4gCj4gPiAKPiA+IFNhbWUgY29tbWVudCBvbiB0aGUgcGF0Y2ggZGVzY3JpcHRpb24g YXMgb24gcGF0Y2ggMi80Lgo+ID4gCj4gPiA+IFNpZ25lZC1vZmYtYnk6IEZyYW5rIExpIDxGcmFu ay5MaUBueHAuY29tPgo+ID4gPiAtLS0KPiA+ID4gCj4gPiA+IE5vdGVzOgo+ID4gPiAgICAgQ2hh bmdlIGZyb20gdjMgdG8gdjQKPiA+ID4gICAgIC0gQ2FsbCBzY2ZnX3BjaWVfc2VuZF90dXJub2Zm X21zZygpIHNoYXJlZCB3aXRoIGxzMTAyMWEKPiA+ID4gICAgIC0gdXBkYXRlIGNvbW1pdCBtZXNz YWdlCj4gPiA+ICAgICAKPiA+ID4gICAgIENoYW5nZSBmcm9tIHYyIHRvIHYzCj4gPiA+ICAgICAt IFJlbW92ZSBsc19wY2llX2x1dF9yZWFkbCh3cml0ZWwpIGZ1bmN0aW9uCj4gPiA+ICAgICAKPiA+ ID4gICAgIENoYW5nZSBmcm9tIHYxIHRvIHYyCj4gPiA+ICAgICAtIFVwZGF0ZSBzdWJqZWN0ICdh JyB0byAnQScKPiA+ID4gCj4gPiA+ICBkcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2ktbGF5 ZXJzY2FwZS5jIHwgNjMgKysrKysrKysrKysrKysrKysrKystCj4gPiA+ICAxIGZpbGUgY2hhbmdl ZCwgNjIgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQo+ID4gPiAKPiA+ID4gZGlmZiAtLWdp dCBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaS1sYXllcnNjYXBlLmMgYi9kcml2ZXJz L3BjaS9jb250cm9sbGVyL2R3Yy9wY2ktbGF5ZXJzY2FwZS5jCj4gPiA+IGluZGV4IDU5MGUwN2Ji MjcwMDIuLmQzOTcwMGIzYWZhYWEgMTAwNjQ0Cj4gPiA+IC0tLSBhL2RyaXZlcnMvcGNpL2NvbnRy b2xsZXIvZHdjL3BjaS1sYXllcnNjYXBlLmMKPiA+ID4gKysrIGIvZHJpdmVycy9wY2kvY29udHJv bGxlci9kd2MvcGNpLWxheWVyc2NhcGUuYwo+ID4gPiBAQCAtNDEsNiArNDEsMTUgQEAKPiA+ID4g ICNkZWZpbmUgU0NGR19QRVhTRlRSU1RDUgkweDE5MAo+ID4gPiAgI2RlZmluZSBQRVhTUihpZHgp CQlCSVQoaWR4KQo+ID4gPiAgCj4gPiA+ICsvKiBMUzEwNDNBIFBFWCBQTUUgY29udHJvbCByZWdp c3RlciAqLwo+ID4gPiArI2RlZmluZSBTQ0ZHX1BFWFBNRUNSCQkweDE0NAo+ID4gPiArI2RlZmlu ZSBQRVhQTUUoaWR4KQkJQklUKDMxIC0gKGlkeCkgKiA0KQo+ID4gPiArCj4gPiA+ICsvKiBMUzEw NDNBIFBFWCBMVVQgZGVidWcgcmVnaXN0ZXIgKi8KPiA+ID4gKyNkZWZpbmUgTFNfUENJRV9MREJH CTB4N2ZjCj4gPiA+ICsjZGVmaW5lIExEQkdfU1IJCUJJVCgzMCkKPiA+ID4gKyNkZWZpbmUgTERC R19XRQkJQklUKDMxKQo+ID4gPiArCj4gPiA+ICAjZGVmaW5lIFBDSUVfSUFUVV9OVU0JCTYKPiA+ ID4gIAo+ID4gPiAgc3RydWN0IGxzX3BjaWVfZHJ2ZGF0YSB7Cj4gPiA+IEBAIC0yMjUsNiArMjM0 LDQ1IEBAIHN0YXRpYyBpbnQgbHMxMDIxYV9wY2llX2V4aXRfZnJvbV9sMihzdHJ1Y3QgZHdfcGNp ZV9ycCAqcHApCj4gPiA+ICAJcmV0dXJuIHNjZmdfcGNpZV9leGl0X2Zyb21fbDIocGNpZS0+c2Nm ZywgU0NGR19QRVhTRlRSU1RDUiwgUEVYU1IocGNpZS0+aW5kZXgpKTsKPiA+ID4gIH0KPiA+ID4g IAo+ID4gPiArc3RhdGljIHZvaWQgbHMxMDQzYV9wY2llX3NlbmRfdHVybm9mZl9tc2coc3RydWN0 IGR3X3BjaWVfcnAgKnBwKQo+ID4gPiArewo+ID4gPiArCXN0cnVjdCBkd19wY2llICpwY2kgPSB0 b19kd19wY2llX2Zyb21fcHAocHApOwo+ID4gPiArCXN0cnVjdCBsc19wY2llICpwY2llID0gdG9f bHNfcGNpZShwY2kpOwo+ID4gPiArCj4gPiA+ICsJc2NmZ19wY2llX3NlbmRfdHVybm9mZl9tc2co cGNpZS0+c2NmZywgU0NGR19QRVhQTUVDUiwgUEVYUE1FKHBjaWUtPmluZGV4KSk7Cj4gPiA+ICt9 Cj4gPiA+ICsKPiA+ID4gK3N0YXRpYyBpbnQgbHMxMDQzYV9wY2llX2V4aXRfZnJvbV9sMihzdHJ1 Y3QgZHdfcGNpZV9ycCAqcHApCj4gPiA+ICt7Cj4gPiA+ICsJc3RydWN0IGR3X3BjaWUgKnBjaSA9 IHRvX2R3X3BjaWVfZnJvbV9wcChwcCk7Cj4gPiA+ICsJc3RydWN0IGxzX3BjaWUgKnBjaWUgPSB0 b19sc19wY2llKHBjaSk7Cj4gPiA+ICsJdTMyIHZhbDsKPiA+ID4gKwo+ID4gPiArCS8qCj4gPiA+ ICsJICogT25seSB3YXkgbGV0IFBFWCBtb2R1bGUgZXhpdCBMMiBpcyBkbyBhIHNvZnR3YXJlIHJl c2V0Lgo+ID4gCj4gPiBDYW4geW91IGV4cGFuZCBQRVg/IFdoYXQgaXMgaXQgdXNlZCBmb3I/Cj4g PiAKPiA+IEFsc28gaWYgdGhlIHJlc2V0IGlzIG9ubHkgZm9yIHRoZSBQRVggbW9kdWxlLCBwbGVh c2UgdXNlIHRoZSBzYW1lIGNvbW1lbnQgaW4KPiA+IGJvdGggcGF0Y2hlcyAyIGFuZCA0LiBQYXRj aCAyIGRvZXNuJ3QgbWVudGlvbiBQRVggaW4gdGhlIGNvbW1lbnQuCj4gCj4gQWZ0ZXIgcmVhZCBz cGVjIGFnYWluLCBJIHRoaW5rIFBFWCBpcyBwY2kgZXhwcmVzcy4gU28gaXQgc2hvdWxkIHNvZnR3 YXJlCj4gcmVzZXQgY29udHJvbGxlci4gSSBkb24ndCBrbm93IHdoYXQgZXhhY3RseSBkaWQgaW4g dGhlIGNoaXAuIEJ1dCB3aXRob3V0Cj4gYmVsb3cgY29kZSwgUENJZSBjYW4ndCBleGl0IEwyL0wz Lgo+IAo+IEFueSBoYXJtZnVsIGlmIGR3YyBjb250cm9sbGVyIHJlc2V0PyBBbnl3YXkgdGhlc2Ug Y29kZSB3b3JrcyB3ZWxsIHdpdGgKPiBpbnRlbCBuZXR3b3JrIGNhcmQuCgpJZiBpdCBpcyBhIERX QyBjb250cm9sbGVyIHJlc2V0LCB0aGVuIHdlIG5lZWQgdG8gcHJvZ3JhbSBhbGwgQ1NScyBsaWtl IERCSQpldGMuLi4gQnV0IGZyb20geW91ciByZXBseSBpdCBzZWVtcyBsaWtlIHRoZSByZXNldCBp cyBsaW1pdGVkIHRvIHNvbWUgbW9kdWxlLApzbyBpdCBpcyBmaW5lLgoKLSBNYW5pCgo+IAo+IEZy YW5rCj4gCj4gPiAKPiA+IC0gTWFuaQo+ID4gCj4gPiA+ICsJICogTERCR19XRTogYWxsb3dzIHRo ZSB1c2VyIHRvIGhhdmUgd3JpdGUgYWNjZXNzIHRvIHRoZSBQRVhEQkdbU1JdIGZvciBib3RoIHNl dHRpbmcgYW5kCj4gPiA+ICsJICoJICAgIGNsZWFyaW5nIHRoZSBzb2Z0IHJlc2V0IG9uIHRoZSBQ RVggbW9kdWxlLgo+ID4gPiArCSAqIExEQkdfU1I6IFdoZW4gU1IgaXMgc2V0IHRvIDEsIHRoZSBQ RVggbW9kdWxlIGVudGVycyBzb2Z0IHJlc2V0Lgo+ID4gPiArCSAqLwo+ID4gPiArCXZhbCA9IGxz X3BjaWVfcGZfbHV0X3JlYWRsKHBjaWUsIExTX1BDSUVfTERCRyk7Cj4gPiA+ICsJdmFsIHw9IExE QkdfV0U7Cj4gPiA+ICsJbHNfcGNpZV9wZl9sdXRfd3JpdGVsKHBjaWUsIExTX1BDSUVfTERCRywg dmFsKTsKPiA+ID4gKwo+ID4gPiArCXZhbCA9IGxzX3BjaWVfcGZfbHV0X3JlYWRsKHBjaWUsIExT X1BDSUVfTERCRyk7Cj4gPiA+ICsJdmFsIHw9IExEQkdfU1I7Cj4gPiA+ICsJbHNfcGNpZV9wZl9s dXRfd3JpdGVsKHBjaWUsIExTX1BDSUVfTERCRywgdmFsKTsKPiA+ID4gKwo+ID4gPiArCXZhbCA9 IGxzX3BjaWVfcGZfbHV0X3JlYWRsKHBjaWUsIExTX1BDSUVfTERCRyk7Cj4gPiA+ICsJdmFsICY9 IH5MREJHX1NSOwo+ID4gPiArCWxzX3BjaWVfcGZfbHV0X3dyaXRlbChwY2llLCBMU19QQ0lFX0xE QkcsIHZhbCk7Cj4gPiA+ICsKPiA+ID4gKwl2YWwgPSBsc19wY2llX3BmX2x1dF9yZWFkbChwY2ll LCBMU19QQ0lFX0xEQkcpOwo+ID4gPiArCXZhbCAmPSB+TERCR19XRTsKPiA+ID4gKwlsc19wY2ll X3BmX2x1dF93cml0ZWwocGNpZSwgTFNfUENJRV9MREJHLCB2YWwpOwo+ID4gPiArCj4gPiA+ICsJ cmV0dXJuIDA7Cj4gPiA+ICt9Cj4gPiA+ICsKPiA+ID4gIHN0YXRpYyBjb25zdCBzdHJ1Y3QgZHdf cGNpZV9ob3N0X29wcyBsc19wY2llX2hvc3Rfb3BzID0gewo+ID4gPiAgCS5ob3N0X2luaXQgPSBs c19wY2llX2hvc3RfaW5pdCwKPiA+ID4gIAkucG1lX3R1cm5fb2ZmID0gbHNfcGNpZV9zZW5kX3R1 cm5vZmZfbXNnLAo+ID4gPiBAQCAtMjQyLDYgKzI5MCwxOSBAQCBzdGF0aWMgY29uc3Qgc3RydWN0 IGxzX3BjaWVfZHJ2ZGF0YSBsczEwMjFhX2RydmRhdGEgPSB7Cj4gPiA+ICAJLmV4aXRfZnJvbV9s MiA9IGxzMTAyMWFfcGNpZV9leGl0X2Zyb21fbDIsCj4gPiA+ICB9Owo+ID4gPiAgCj4gPiA+ICtz dGF0aWMgY29uc3Qgc3RydWN0IGR3X3BjaWVfaG9zdF9vcHMgbHMxMDQzYV9wY2llX2hvc3Rfb3Bz ID0gewo+ID4gPiArCS5ob3N0X2luaXQgPSBsc19wY2llX2hvc3RfaW5pdCwKPiA+ID4gKwkucG1l X3R1cm5fb2ZmID0gbHMxMDQzYV9wY2llX3NlbmRfdHVybm9mZl9tc2csCj4gPiA+ICt9Owo+ID4g PiArCj4gPiA+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGxzX3BjaWVfZHJ2ZGF0YSBsczEwNDNhX2Ry dmRhdGEgPSB7Cj4gPiA+ICsJLnBmX2x1dF9vZmYgPSAweDEwMDAwLAo+ID4gPiArCS5wbV9zdXBw b3J0ID0gdHJ1ZSwKPiA+ID4gKwkuc2NmZ19zdXBwb3J0ID0gdHJ1ZSwKPiA+ID4gKwkub3BzID0g JmxzMTA0M2FfcGNpZV9ob3N0X29wcywKPiA+ID4gKwkuZXhpdF9mcm9tX2wyID0gbHMxMDQzYV9w Y2llX2V4aXRfZnJvbV9sMiwKPiA+ID4gK307Cj4gPiA+ICsKPiA+ID4gIHN0YXRpYyBjb25zdCBz dHJ1Y3QgbHNfcGNpZV9kcnZkYXRhIGxheWVyc2NhcGVfZHJ2ZGF0YSA9IHsKPiA+ID4gIAkucGZf bHV0X29mZiA9IDB4YzAwMDAsCj4gPiA+ICAJLnBtX3N1cHBvcnQgPSB0cnVlLAo+ID4gPiBAQCAt MjUyLDcgKzMxMyw3IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIGxzX3BjaWVf b2ZfbWF0Y2hbXSA9IHsKPiA+ID4gIAl7IC5jb21wYXRpYmxlID0gImZzbCxsczEwMTJhLXBjaWUi LCAuZGF0YSA9ICZsYXllcnNjYXBlX2RydmRhdGEgfSwKPiA+ID4gIAl7IC5jb21wYXRpYmxlID0g ImZzbCxsczEwMjFhLXBjaWUiLCAuZGF0YSA9ICZsczEwMjFhX2RydmRhdGEgfSwKPiA+ID4gIAl7 IC5jb21wYXRpYmxlID0gImZzbCxsczEwMjhhLXBjaWUiLCAuZGF0YSA9ICZsYXllcnNjYXBlX2Ry dmRhdGEgfSwKPiA+ID4gLQl7IC5jb21wYXRpYmxlID0gImZzbCxsczEwNDNhLXBjaWUiLCAuZGF0 YSA9ICZsczEwMjFhX2RydmRhdGEgfSwKPiA+ID4gKwl7IC5jb21wYXRpYmxlID0gImZzbCxsczEw NDNhLXBjaWUiLCAuZGF0YSA9ICZsczEwNDNhX2RydmRhdGEgfSwKPiA+ID4gIAl7IC5jb21wYXRp YmxlID0gImZzbCxsczEwNDZhLXBjaWUiLCAuZGF0YSA9ICZsYXllcnNjYXBlX2RydmRhdGEgfSwK PiA+ID4gIAl7IC5jb21wYXRpYmxlID0gImZzbCxsczIwODBhLXBjaWUiLCAuZGF0YSA9ICZsYXll cnNjYXBlX2RydmRhdGEgfSwKPiA+ID4gIAl7IC5jb21wYXRpYmxlID0gImZzbCxsczIwODVhLXBj aWUiLCAuZGF0YSA9ICZsYXllcnNjYXBlX2RydmRhdGEgfSwKPiA+ID4gLS0gCj4gPiA+IDIuMzQu MQo+ID4gPiAKPiA+IAo+ID4gLS0gCj4gPiDgrq7grqPgrr/grrXgrqPgr43grqPgrqngr40g4K6a 4K6k4K6+4K6a4K6/4K614K6u4K+NCgotLSAK4K6u4K6j4K6/4K614K6j4K+N4K6j4K6p4K+NIOCu muCupOCuvuCumuCuv+CuteCuruCvjQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtl cm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxt YW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=