From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-vk1-f175.google.com (mail-vk1-f175.google.com [209.85.221.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFC581C6B6 for ; Mon, 4 Dec 2023 10:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="I1yfZKzm" Received: by mail-vk1-f175.google.com with SMTP id 71dfb90a1353d-4b2ee700323so52673e0c.3 for ; Mon, 04 Dec 2023 02:59:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701687581; x=1702292381; darn=lists.linux.dev; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=7bEx0tCg0pBB2RGpWhKyVXvpL7LgHhHvq8+rdmdgSd4=; b=I1yfZKzm4FSKP4jQfsx+GEokY2WjwyF6/Z+7s07RHYt/2rAeEPQFA/87eG+E4FaXnQ DhJgF/+192lbezlKOulNeCxBPnI/a65uF1/410m1haIJa1MO4cyFknKQEnDSlzaCt5rl G6Yx6eKdMc/MhV0fAlakA757VaUkjD9bEACfty0Va1E2IzLY9wfIxWqjW0eTgcd/Yxj8 oAra9IjNCC4TO7YZgQhR/Ttny4Ium9Xp5SqgFyp5Ha+5esV8fihGxP5Ohfs/N7rEYoJO PVBaQSDTLvicQjw503PhnwasTfI06/VZ9ACkTjDpYe9htA96T4QA0/Iqw3utcjRefKeF Gkyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701687581; x=1702292381; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7bEx0tCg0pBB2RGpWhKyVXvpL7LgHhHvq8+rdmdgSd4=; b=R/ryvWM5f0mtCA/iiPVCgD5HkxWsZOWTKqCE9ryMdF1zYRJ3TqHctdTRHOMwwsox4O GRlCzvkxWBV8Kt5agIv0ISWT8HgEkf/dc/+ovFJsp2LGjQZRcwt15U/x0xZz+uh1lm+t 0l5L6t36qpgrf9+eqx4+68g5laA9J2xQwcuDSSp8eDxkEinMUJFTXps5PfYPpU47AtOd z6Rb/NuWWkqzoZZEtaS9O4HeBwRgs7ScgfDllTCg0OKPTilRHDlIXgi4/jIbt8UiqkNf nf2vSi69FN+pBtqMiFcdkEYgNydJZekYe35xp/7FpnErF6JAN8nyGOuv7phYQqufpZBK /xrg== X-Gm-Message-State: AOJu0Yy1zh6PuNeJ6yUOJ4IHxVhPz6sv66VMiaEMc8vaCaO2bfiNwTe7 8pORfqYnvyzH09x72ogLRYs8 X-Google-Smtp-Source: AGHT+IHaxXfyDhijP6/BJkFg6aoA3IV347qjEa/qt4rjuAXnbel85JEDfVEpxBpRpyh9yIkK0iQFMw== X-Received: by 2002:ac5:cfed:0:b0:4b2:c554:eeff with SMTP id m45-20020ac5cfed000000b004b2c554eeffmr1436442vkf.17.1701687581647; Mon, 04 Dec 2023 02:59:41 -0800 (PST) Received: from thinkpad ([117.213.101.240]) by smtp.gmail.com with ESMTPSA id k13-20020a05620a07ed00b0077d61831eb2sm4137123qkk.40.2023.12.04.02.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 02:59:41 -0800 (PST) Date: Mon, 4 Dec 2023 16:29:31 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: Re: [PATCH v5 2/4] PCI: layerscape: Add suspend/resume for ls1021a Message-ID: <20231204105931.GB35383@thinkpad> References: <20231201161712.1645987-1-Frank.Li@nxp.com> <20231201161712.1645987-3-Frank.Li@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20231201161712.1645987-3-Frank.Li@nxp.com> On Fri, Dec 01, 2023 at 11:17:10AM -0500, Frank Li wrote: > Add suspend/resume support for Layerscape LS1021a. > > In the suspend path, PME_Turn_Off message is sent to the endpoint to > transition the link to L2/L3_Ready state. In this SoC, there is no way to > check if the controller has received the PME_To_Ack from the endpoint or > not. So to be on the safer side, the driver just waits for > PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF > bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3 > state depending on the VAUX supply. > > In the resume path, the link is brought back from L2 to L0 by doing a > software reset. > > Signed-off-by: Frank Li One comment below. With that addressed, Reviewed-by: Manivannan Sadhasivam > --- > > Notes: > Change from v4 to v5 > - update comit message > - remove a empty line > - use comments > /* Reset the PEX wrapper to bring the link out of L2 */ > - pci->pp.ops = pcie->drvdata->ops, > ls_pcie_host_ops to the "ops" member of layerscape_drvdata. > - don't set pcie->scfg = NULL at error path > > Change from v3 to v4 > - update commit message. > - it is reset a glue logic part for PCI controller. > - use regmap_write_bits() to reduce code change. > > Change from v2 to v3 > - update according to mani's feedback > change from v1 to v2 > - change subject 'a' to 'A' > > drivers/pci/controller/dwc/pci-layerscape.c | 81 ++++++++++++++++++++- > 1 file changed, 80 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > index aea89926bcc4f..8bdaae9be7d56 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape.c > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > @@ -35,11 +35,19 @@ > #define PF_MCR_PTOMR BIT(0) > #define PF_MCR_EXL2S BIT(1) > > +/* LS1021A PEXn PM Write Control Register */ > +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) > +#define PMXMTTURNOFF BIT(31) > +#define SCFG_PEXSFTRSTCR 0x190 > +#define PEXSR(idx) BIT(idx) > + > #define PCIE_IATU_NUM 6 > > struct ls_pcie_drvdata { > const u32 pf_off; > + const struct dw_pcie_host_ops *ops; > int (*exit_from_l2)(struct dw_pcie_rp *pp); > + bool scfg_support; > bool pm_support; > }; > > @@ -47,6 +55,8 @@ struct ls_pcie { > struct dw_pcie *pci; > const struct ls_pcie_drvdata *drvdata; > void __iomem *pf_base; > + struct regmap *scfg; > + int index; > bool big_endian; > }; > > @@ -171,18 +181,70 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) > return 0; > } > > +static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask) > +{ > + /* Send PME_Turn_Off message */ > + regmap_write_bits(scfg, reg, mask, mask); > + > + /* > + * There is no specific register to check for PME_To_Ack from endpoint. > + * So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US. > + */ > + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); > + > + /* > + * Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit > + * to complete the PME_Turn_Off handshake. > + */ > + regmap_write_bits(scfg, reg, mask, 0); > +} > + > +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + > + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF); > +} > + > +static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask) > +{ > + /* Reset the PEX wrapper to bring the link out of L2 */ > + regmap_write_bits(scfg, reg, mask, mask); > + regmap_write_bits(scfg, reg, mask, 0); > + > + return 0; > +} > + > +static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + > + return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); > +} > + > static const struct dw_pcie_host_ops ls_pcie_host_ops = { > .host_init = ls_pcie_host_init, > .pme_turn_off = ls_pcie_send_turnoff_msg, > }; > > +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { > + .host_init = ls_pcie_host_init, > + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, > +}; > + > static const struct ls_pcie_drvdata ls1021a_drvdata = { > - .pm_support = false, > + .pm_support = true, > + .scfg_support = true, > + .ops = &ls1021a_pcie_host_ops, > + .exit_from_l2 = ls1021a_pcie_exit_from_l2, > }; > > static const struct ls_pcie_drvdata layerscape_drvdata = { > .pf_off = 0xc0000, > .pm_support = true, > + .ops = &ls_pcie_host_ops; > .exit_from_l2 = ls_pcie_exit_from_l2, > }; > > @@ -205,6 +267,8 @@ static int ls_pcie_probe(struct platform_device *pdev) > struct dw_pcie *pci; > struct ls_pcie *pcie; > struct resource *dbi_base; > + u32 index[2]; > + int ret; > > pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > if (!pcie) > @@ -220,6 +284,7 @@ static int ls_pcie_probe(struct platform_device *pdev) > pci->pp.ops = &ls_pcie_host_ops; This should be removed now. - Mani > > pcie->pci = pci; > + pci->pp.ops = pcie->drvdata->ops; > > dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); > pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); > @@ -230,6 +295,20 @@ static int ls_pcie_probe(struct platform_device *pdev) > > pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; > > + if (pcie->drvdata->scfg_support) { > + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); > + if (IS_ERR(pcie->scfg)) { > + dev_err(dev, "No syscfg phandle specified\n"); > + return PTR_ERR(pcie->scfg); > + } > + > + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); > + if (ret) > + return ret; > + > + pcie->index = index[1]; > + } > + > if (!ls_pcie_is_bridge(pcie)) > return -ENODEV; > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C69FC10F04 for ; Mon, 4 Dec 2023 11:00:41 +0000 (UTC) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Ju1pMtt2; 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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20231201161712.1645987-3-Frank.Li@nxp.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: imx@lists.linux.dev, kw@linux.com, linux-pci@vger.kernel.org, lpieralisi@kernel.org, linux-kernel@vger.kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, bhelgaas@google.com, linuxppc-dev@lists.ozlabs.org, robh@kernel.org, linux-arm-kernel@lists.infradead.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, Dec 01, 2023 at 11:17:10AM -0500, Frank Li wrote: > Add suspend/resume support for Layerscape LS1021a. > > In the suspend path, PME_Turn_Off message is sent to the endpoint to > transition the link to L2/L3_Ready state. In this SoC, there is no way to > check if the controller has received the PME_To_Ack from the endpoint or > not. So to be on the safer side, the driver just waits for > PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF > bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3 > state depending on the VAUX supply. > > In the resume path, the link is brought back from L2 to L0 by doing a > software reset. > > Signed-off-by: Frank Li One comment below. With that addressed, Reviewed-by: Manivannan Sadhasivam > --- > > Notes: > Change from v4 to v5 > - update comit message > - remove a empty line > - use comments > /* Reset the PEX wrapper to bring the link out of L2 */ > - pci->pp.ops = pcie->drvdata->ops, > ls_pcie_host_ops to the "ops" member of layerscape_drvdata. > - don't set pcie->scfg = NULL at error path > > Change from v3 to v4 > - update commit message. > - it is reset a glue logic part for PCI controller. > - use regmap_write_bits() to reduce code change. > > Change from v2 to v3 > - update according to mani's feedback > change from v1 to v2 > - change subject 'a' to 'A' > > drivers/pci/controller/dwc/pci-layerscape.c | 81 ++++++++++++++++++++- > 1 file changed, 80 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > index aea89926bcc4f..8bdaae9be7d56 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape.c > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > @@ -35,11 +35,19 @@ > #define PF_MCR_PTOMR BIT(0) > #define PF_MCR_EXL2S BIT(1) > > +/* LS1021A PEXn PM Write Control Register */ > +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) > +#define PMXMTTURNOFF BIT(31) > +#define SCFG_PEXSFTRSTCR 0x190 > +#define PEXSR(idx) BIT(idx) > + > #define PCIE_IATU_NUM 6 > > struct ls_pcie_drvdata { > const u32 pf_off; > + const struct dw_pcie_host_ops *ops; > int (*exit_from_l2)(struct dw_pcie_rp *pp); > + bool scfg_support; > bool pm_support; > }; > > @@ -47,6 +55,8 @@ struct ls_pcie { > struct dw_pcie *pci; > const struct ls_pcie_drvdata *drvdata; > void __iomem *pf_base; > + struct regmap *scfg; > + int index; > bool big_endian; > }; > > @@ -171,18 +181,70 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) > return 0; > } > > +static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask) > +{ > + /* Send PME_Turn_Off message */ > + regmap_write_bits(scfg, reg, mask, mask); > + > + /* > + * There is no specific register to check for PME_To_Ack from endpoint. > + * So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US. > + */ > + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); > + > + /* > + * Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit > + * to complete the PME_Turn_Off handshake. > + */ > + regmap_write_bits(scfg, reg, mask, 0); > +} > + > +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + > + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF); > +} > + > +static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask) > +{ > + /* Reset the PEX wrapper to bring the link out of L2 */ > + regmap_write_bits(scfg, reg, mask, mask); > + regmap_write_bits(scfg, reg, mask, 0); > + > + return 0; > +} > + > +static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + > + return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); > +} > + > static const struct dw_pcie_host_ops ls_pcie_host_ops = { > .host_init = ls_pcie_host_init, > .pme_turn_off = ls_pcie_send_turnoff_msg, > }; > > +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { > + .host_init = ls_pcie_host_init, > + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, > +}; > + > static const struct ls_pcie_drvdata ls1021a_drvdata = { > - .pm_support = false, > + .pm_support = true, > + .scfg_support = true, > + .ops = &ls1021a_pcie_host_ops, > + .exit_from_l2 = ls1021a_pcie_exit_from_l2, > }; > > static const struct ls_pcie_drvdata layerscape_drvdata = { > .pf_off = 0xc0000, > .pm_support = true, > + .ops = &ls_pcie_host_ops; > .exit_from_l2 = ls_pcie_exit_from_l2, > }; > > @@ -205,6 +267,8 @@ static int ls_pcie_probe(struct platform_device *pdev) > struct dw_pcie *pci; > struct ls_pcie *pcie; > struct resource *dbi_base; > + u32 index[2]; > + int ret; > > pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > if (!pcie) > @@ -220,6 +284,7 @@ static int ls_pcie_probe(struct platform_device *pdev) > pci->pp.ops = &ls_pcie_host_ops; This should be removed now. - Mani > > pcie->pci = pci; > + pci->pp.ops = pcie->drvdata->ops; > > dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); > pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); > @@ -230,6 +295,20 @@ static int ls_pcie_probe(struct platform_device *pdev) > > pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; > > + if (pcie->drvdata->scfg_support) { > + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); > + if (IS_ERR(pcie->scfg)) { > + dev_err(dev, "No syscfg phandle specified\n"); > + return PTR_ERR(pcie->scfg); > + } > + > + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); > + if (ret) > + return ret; > + > + pcie->index = index[1]; > + } > + > if (!ls_pcie_is_bridge(pcie)) > return -ENODEV; > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95C87C4167B for ; Mon, 4 Dec 2023 11:00:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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16:29:31 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: Re: [PATCH v5 2/4] PCI: layerscape: Add suspend/resume for ls1021a Message-ID: <20231204105931.GB35383@thinkpad> References: <20231201161712.1645987-1-Frank.Li@nxp.com> <20231201161712.1645987-3-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231201161712.1645987-3-Frank.Li@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231204_025943_570416_D1E1FEE2 X-CRM114-Status: GOOD ( 36.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gRnJpLCBEZWMgMDEsIDIwMjMgYXQgMTE6MTc6MTBBTSAtMDUwMCwgRnJhbmsgTGkgd3JvdGU6 Cj4gQWRkIHN1c3BlbmQvcmVzdW1lIHN1cHBvcnQgZm9yIExheWVyc2NhcGUgTFMxMDIxYS4KPiAK PiBJbiB0aGUgc3VzcGVuZCBwYXRoLCBQTUVfVHVybl9PZmYgbWVzc2FnZSBpcyBzZW50IHRvIHRo ZSBlbmRwb2ludCB0bwo+IHRyYW5zaXRpb24gdGhlIGxpbmsgdG8gTDIvTDNfUmVhZHkgc3RhdGUu IEluIHRoaXMgU29DLCB0aGVyZSBpcyBubyB3YXkgdG8KPiBjaGVjayBpZiB0aGUgY29udHJvbGxl ciBoYXMgcmVjZWl2ZWQgdGhlIFBNRV9Ub19BY2sgZnJvbSB0aGUgZW5kcG9pbnQgb3IKPiBub3Qu IFNvIHRvIGJlIG9uIHRoZSBzYWZlciBzaWRlLCB0aGUgZHJpdmVyIGp1c3Qgd2FpdHMgZm9yCj4g UENJRV9QTUVfVE9fTDJfVElNRU9VVF9VUyBiZWZvcmUgYXNzZXJ0aW5nIHRoZSBTb0Mgc3BlY2lm aWMgUE1YTVRUVVJOT0ZGCj4gYml0IHRvIGNvbXBsZXRlIHRoZSBQTUVfVHVybl9PZmYgaGFuZHNo YWtlLiBUaGVuIHRoZSBsaW5rIHdvdWxkIGVudGVyIEwyL0wzCj4gc3RhdGUgZGVwZW5kaW5nIG9u IHRoZSBWQVVYIHN1cHBseS4KPiAKPiBJbiB0aGUgcmVzdW1lIHBhdGgsIHRoZSBsaW5rIGlzIGJy b3VnaHQgYmFjayBmcm9tIEwyIHRvIEwwIGJ5IGRvaW5nIGEKPiBzb2Z0d2FyZSByZXNldC4KPiAK PiBTaWduZWQtb2ZmLWJ5OiBGcmFuayBMaSA8RnJhbmsuTGlAbnhwLmNvbT4KCk9uZSBjb21tZW50 IGJlbG93LiBXaXRoIHRoYXQgYWRkcmVzc2VkLAoKUmV2aWV3ZWQtYnk6IE1hbml2YW5uYW4gU2Fk aGFzaXZhbSA8bWFuaXZhbm5hbi5zYWRoYXNpdmFtQGxpbmFyby5vcmc+Cgo+IC0tLQo+IAo+IE5v dGVzOgo+ICAgICBDaGFuZ2UgZnJvbSB2NCB0byB2NQo+ICAgICAtIHVwZGF0ZSBjb21pdCBtZXNz YWdlCj4gICAgIC0gcmVtb3ZlIGEgZW1wdHkgbGluZQo+ICAgICAtIHVzZSBjb21tZW50cwo+ICAg ICAvKiBSZXNldCB0aGUgUEVYIHdyYXBwZXIgdG8gYnJpbmcgdGhlIGxpbmsgb3V0IG9mIEwyICov Cj4gICAgIC0gcGNpLT5wcC5vcHMgPSBwY2llLT5kcnZkYXRhLT5vcHMsCj4gICAgIGxzX3BjaWVf aG9zdF9vcHMgdG8gdGhlICJvcHMiIG1lbWJlciBvZiBsYXllcnNjYXBlX2RydmRhdGEuCj4gICAg IC0gZG9uJ3Qgc2V0IHBjaWUtPnNjZmcgPSBOVUxMIGF0IGVycm9yIHBhdGgKPiAgICAgCj4gICAg IENoYW5nZSBmcm9tIHYzIHRvIHY0Cj4gICAgIC0gdXBkYXRlIGNvbW1pdCBtZXNzYWdlLgo+ICAg ICAtIGl0IGlzIHJlc2V0IGEgZ2x1ZSBsb2dpYyBwYXJ0IGZvciBQQ0kgY29udHJvbGxlci4KPiAg ICAgLSB1c2UgcmVnbWFwX3dyaXRlX2JpdHMoKSB0byByZWR1Y2UgY29kZSBjaGFuZ2UuCj4gICAg IAo+ICAgICBDaGFuZ2UgZnJvbSB2MiB0byB2Mwo+ICAgICAtIHVwZGF0ZSBhY2NvcmRpbmcgdG8g bWFuaSdzIGZlZWRiYWNrCj4gICAgIGNoYW5nZSBmcm9tIHYxIHRvIHYyCj4gICAgIC0gY2hhbmdl IHN1YmplY3QgJ2EnIHRvICdBJwo+IAo+ICBkcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2kt bGF5ZXJzY2FwZS5jIHwgODEgKysrKysrKysrKysrKysrKysrKystCj4gIDEgZmlsZSBjaGFuZ2Vk LCA4MCBpbnNlcnRpb25zKCspLCAxIGRlbGV0aW9uKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZl cnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaS1sYXllcnNjYXBlLmMgYi9kcml2ZXJzL3BjaS9jb250 cm9sbGVyL2R3Yy9wY2ktbGF5ZXJzY2FwZS5jCj4gaW5kZXggYWVhODk5MjZiY2M0Zi4uOGJkYWFl OWJlN2Q1NiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2ktbGF5 ZXJzY2FwZS5jCj4gKysrIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpLWxheWVyc2Nh cGUuYwo+IEBAIC0zNSwxMSArMzUsMTkgQEAKPiAgI2RlZmluZSBQRl9NQ1JfUFRPTVIJCUJJVCgw KQo+ICAjZGVmaW5lIFBGX01DUl9FWEwyUwkJQklUKDEpCj4gIAo+ICsvKiBMUzEwMjFBIFBFWG4g UE0gV3JpdGUgQ29udHJvbCBSZWdpc3RlciAqLwo+ICsjZGVmaW5lIFNDRkdfUEVYUE1XUkNSKGlk eCkJKDB4NWMgKyAoaWR4KSAqIDB4NjQpCj4gKyNkZWZpbmUgUE1YTVRUVVJOT0ZGCQlCSVQoMzEp Cj4gKyNkZWZpbmUgU0NGR19QRVhTRlRSU1RDUgkweDE5MAo+ICsjZGVmaW5lIFBFWFNSKGlkeCkJ CUJJVChpZHgpCj4gKwo+ICAjZGVmaW5lIFBDSUVfSUFUVV9OVU0JCTYKPiAgCj4gIHN0cnVjdCBs c19wY2llX2RydmRhdGEgewo+ICAJY29uc3QgdTMyIHBmX29mZjsKPiArCWNvbnN0IHN0cnVjdCBk d19wY2llX2hvc3Rfb3BzICpvcHM7Cj4gIAlpbnQgKCpleGl0X2Zyb21fbDIpKHN0cnVjdCBkd19w Y2llX3JwICpwcCk7Cj4gKwlib29sIHNjZmdfc3VwcG9ydDsKPiAgCWJvb2wgcG1fc3VwcG9ydDsK PiAgfTsKPiAgCj4gQEAgLTQ3LDYgKzU1LDggQEAgc3RydWN0IGxzX3BjaWUgewo+ICAJc3RydWN0 IGR3X3BjaWUgKnBjaTsKPiAgCWNvbnN0IHN0cnVjdCBsc19wY2llX2RydmRhdGEgKmRydmRhdGE7 Cj4gIAl2b2lkIF9faW9tZW0gKnBmX2Jhc2U7Cj4gKwlzdHJ1Y3QgcmVnbWFwICpzY2ZnOwo+ICsJ aW50IGluZGV4Owo+ICAJYm9vbCBiaWdfZW5kaWFuOwo+ICB9Owo+ICAKPiBAQCAtMTcxLDE4ICsx ODEsNzAgQEAgc3RhdGljIGludCBsc19wY2llX2hvc3RfaW5pdChzdHJ1Y3QgZHdfcGNpZV9ycCAq cHApCj4gIAlyZXR1cm4gMDsKPiAgfQo+ICAKPiArc3RhdGljIHZvaWQgc2NmZ19wY2llX3NlbmRf dHVybm9mZl9tc2coc3RydWN0IHJlZ21hcCAqc2NmZywgdTMyIHJlZywgdTMyIG1hc2spCj4gK3sK PiArCS8qIFNlbmQgUE1FX1R1cm5fT2ZmIG1lc3NhZ2UgKi8KPiArCXJlZ21hcF93cml0ZV9iaXRz KHNjZmcsIHJlZywgbWFzaywgbWFzayk7Cj4gKwo+ICsJLyoKPiArCSAqIFRoZXJlIGlzIG5vIHNw ZWNpZmljIHJlZ2lzdGVyIHRvIGNoZWNrIGZvciBQTUVfVG9fQWNrIGZyb20gZW5kcG9pbnQuCj4g KwkgKiBTbyBvbiB0aGUgc2FmZSBzaWRlLCB3YWl0IGZvciBQQ0lFX1BNRV9UT19MMl9USU1FT1VU X1VTLgo+ICsJICovCj4gKwltZGVsYXkoUENJRV9QTUVfVE9fTDJfVElNRU9VVF9VUy8xMDAwKTsK PiArCj4gKwkvKgo+ICsJICogTGF5ZXJzY2FwZSBoYXJkd2FyZSByZWZlcmVuY2UgbWFudWFsIHJl Y29tbWVuZHMgY2xlYXJpbmcgdGhlIFBNWE1UVFVSTk9GRiBiaXQKPiArCSAqIHRvIGNvbXBsZXRl IHRoZSBQTUVfVHVybl9PZmYgaGFuZHNoYWtlLgo+ICsJICovCj4gKwlyZWdtYXBfd3JpdGVfYml0 cyhzY2ZnLCByZWcsIG1hc2ssIDApOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBsczEwMjFhX3Bj aWVfc2VuZF90dXJub2ZmX21zZyhzdHJ1Y3QgZHdfcGNpZV9ycCAqcHApCj4gK3sKPiArCXN0cnVj dCBkd19wY2llICpwY2kgPSB0b19kd19wY2llX2Zyb21fcHAocHApOwo+ICsJc3RydWN0IGxzX3Bj aWUgKnBjaWUgPSB0b19sc19wY2llKHBjaSk7Cj4gKwo+ICsJc2NmZ19wY2llX3NlbmRfdHVybm9m Zl9tc2cocGNpZS0+c2NmZywgU0NGR19QRVhQTVdSQ1IocGNpZS0+aW5kZXgpLCBQTVhNVFRVUk5P RkYpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IHNjZmdfcGNpZV9leGl0X2Zyb21fbDIoc3RydWN0 IHJlZ21hcCAqc2NmZywgdTMyIHJlZywgdTMyIG1hc2spCj4gK3sKPiArCS8qIFJlc2V0IHRoZSBQ RVggd3JhcHBlciB0byBicmluZyB0aGUgbGluayBvdXQgb2YgTDIgKi8KPiArCXJlZ21hcF93cml0 ZV9iaXRzKHNjZmcsIHJlZywgbWFzaywgbWFzayk7Cj4gKwlyZWdtYXBfd3JpdGVfYml0cyhzY2Zn LCByZWcsIG1hc2ssIDApOwo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50 IGxzMTAyMWFfcGNpZV9leGl0X2Zyb21fbDIoc3RydWN0IGR3X3BjaWVfcnAgKnBwKQo+ICt7Cj4g KwlzdHJ1Y3QgZHdfcGNpZSAqcGNpID0gdG9fZHdfcGNpZV9mcm9tX3BwKHBwKTsKPiArCXN0cnVj dCBsc19wY2llICpwY2llID0gdG9fbHNfcGNpZShwY2kpOwo+ICsKPiArCXJldHVybiBzY2ZnX3Bj aWVfZXhpdF9mcm9tX2wyKHBjaWUtPnNjZmcsIFNDRkdfUEVYU0ZUUlNUQ1IsIFBFWFNSKHBjaWUt PmluZGV4KSk7Cj4gK30KPiArCj4gIHN0YXRpYyBjb25zdCBzdHJ1Y3QgZHdfcGNpZV9ob3N0X29w cyBsc19wY2llX2hvc3Rfb3BzID0gewo+ICAJLmhvc3RfaW5pdCA9IGxzX3BjaWVfaG9zdF9pbml0 LAo+ICAJLnBtZV90dXJuX29mZiA9IGxzX3BjaWVfc2VuZF90dXJub2ZmX21zZywKPiAgfTsKPiAg Cj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgZHdfcGNpZV9ob3N0X29wcyBsczEwMjFhX3BjaWVfaG9z dF9vcHMgPSB7Cj4gKwkuaG9zdF9pbml0ID0gbHNfcGNpZV9ob3N0X2luaXQsCj4gKwkucG1lX3R1 cm5fb2ZmID0gbHMxMDIxYV9wY2llX3NlbmRfdHVybm9mZl9tc2csCj4gK307Cj4gKwo+ICBzdGF0 aWMgY29uc3Qgc3RydWN0IGxzX3BjaWVfZHJ2ZGF0YSBsczEwMjFhX2RydmRhdGEgPSB7Cj4gLQku cG1fc3VwcG9ydCA9IGZhbHNlLAo+ICsJLnBtX3N1cHBvcnQgPSB0cnVlLAo+ICsJLnNjZmdfc3Vw cG9ydCA9IHRydWUsCj4gKwkub3BzID0gJmxzMTAyMWFfcGNpZV9ob3N0X29wcywKPiArCS5leGl0 X2Zyb21fbDIgPSBsczEwMjFhX3BjaWVfZXhpdF9mcm9tX2wyLAo+ICB9Owo+ICAKPiAgc3RhdGlj IGNvbnN0IHN0cnVjdCBsc19wY2llX2RydmRhdGEgbGF5ZXJzY2FwZV9kcnZkYXRhID0gewo+ICAJ LnBmX29mZiA9IDB4YzAwMDAsCj4gIAkucG1fc3VwcG9ydCA9IHRydWUsCj4gKwkub3BzID0gJmxz X3BjaWVfaG9zdF9vcHM7Cj4gIAkuZXhpdF9mcm9tX2wyID0gbHNfcGNpZV9leGl0X2Zyb21fbDIs Cj4gIH07Cj4gIAo+IEBAIC0yMDUsNiArMjY3LDggQEAgc3RhdGljIGludCBsc19wY2llX3Byb2Jl KHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4gIAlzdHJ1Y3QgZHdfcGNpZSAqcGNpOwo+ ICAJc3RydWN0IGxzX3BjaWUgKnBjaWU7Cj4gIAlzdHJ1Y3QgcmVzb3VyY2UgKmRiaV9iYXNlOwo+ ICsJdTMyIGluZGV4WzJdOwo+ICsJaW50IHJldDsKPiAgCj4gIAlwY2llID0gZGV2bV9remFsbG9j KGRldiwgc2l6ZW9mKCpwY2llKSwgR0ZQX0tFUk5FTCk7Cj4gIAlpZiAoIXBjaWUpCj4gQEAgLTIy MCw2ICsyODQsNyBAQCBzdGF0aWMgaW50IGxzX3BjaWVfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2Rl dmljZSAqcGRldikKPiAgCXBjaS0+cHAub3BzID0gJmxzX3BjaWVfaG9zdF9vcHM7CgpUaGlzIHNo b3VsZCBiZSByZW1vdmVkIG5vdy4KCi0gTWFuaQoKPiAgCj4gIAlwY2llLT5wY2kgPSBwY2k7Cj4g KwlwY2ktPnBwLm9wcyA9IHBjaWUtPmRydmRhdGEtPm9wczsKPiAgCj4gIAlkYmlfYmFzZSA9IHBs YXRmb3JtX2dldF9yZXNvdXJjZV9ieW5hbWUocGRldiwgSU9SRVNPVVJDRV9NRU0sICJyZWdzIik7 Cj4gIAlwY2ktPmRiaV9iYXNlID0gZGV2bV9wY2lfcmVtYXBfY2ZnX3Jlc291cmNlKGRldiwgZGJp X2Jhc2UpOwo+IEBAIC0yMzAsNiArMjk1LDIwIEBAIHN0YXRpYyBpbnQgbHNfcGNpZV9wcm9iZShz dHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+ICAKPiAgCXBjaWUtPnBmX2Jhc2UgPSBwY2kt PmRiaV9iYXNlICsgcGNpZS0+ZHJ2ZGF0YS0+cGZfb2ZmOwo+ICAKPiArCWlmIChwY2llLT5kcnZk YXRhLT5zY2ZnX3N1cHBvcnQpIHsKPiArCQlwY2llLT5zY2ZnID0gc3lzY29uX3JlZ21hcF9sb29r dXBfYnlfcGhhbmRsZShkZXYtPm9mX25vZGUsICJmc2wscGNpZS1zY2ZnIik7Cj4gKwkJaWYgKElT X0VSUihwY2llLT5zY2ZnKSkgewo+ICsJCQlkZXZfZXJyKGRldiwgIk5vIHN5c2NmZyBwaGFuZGxl IHNwZWNpZmllZFxuIik7Cj4gKwkJCXJldHVybiBQVFJfRVJSKHBjaWUtPnNjZmcpOwo+ICsJCX0K PiArCj4gKwkJcmV0ID0gb2ZfcHJvcGVydHlfcmVhZF91MzJfYXJyYXkoZGV2LT5vZl9ub2RlLCAi ZnNsLHBjaWUtc2NmZyIsIGluZGV4LCAyKTsKPiArCQlpZiAocmV0KQo+ICsJCQlyZXR1cm4gcmV0 Owo+ICsKPiArCQlwY2llLT5pbmRleCA9IGluZGV4WzFdOwo+ICsJfQo+ICsKPiAgCWlmICghbHNf cGNpZV9pc19icmlkZ2UocGNpZSkpCj4gIAkJcmV0dXJuIC1FTk9ERVY7Cj4gIAo+IC0tIAo+IDIu MzQuMQo+IAoKLS0gCuCuruCuo+Cuv+CuteCuo+CvjeCuo+CuqeCvjSDgrprgrqTgrr7grprgrr/g rrXgrq7gr40KCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f CmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5m cmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xp bnV4LWFybS1rZXJuZWwK