From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AE14144C9E for ; Thu, 7 Dec 2023 17:12:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 63C48153B; Thu, 7 Dec 2023 09:13:30 -0800 (PST) Received: from e124191.cambridge.arm.com (e124191.cambridge.arm.com [10.1.197.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E54573F762; Thu, 7 Dec 2023 09:12:42 -0800 (PST) Date: Thu, 7 Dec 2023 17:12:37 +0000 From: Joey Gouly To: Fuad Tabba Cc: kvmarm@lists.linux.dev, maz@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, eric.auger@redhat.com, jingzhangos@google.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 06/12] KVM: arm64: Update and fix FGT register masks Message-ID: <20231207171237.GA87398@e124191.cambridge.arm.com> References: <20231206100503.564090-1-tabba@google.com> <20231206100503.564090-7-tabba@google.com> <20231207150001.GA29745@e124191.cambridge.arm.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Thu, Dec 07, 2023 at 03:06:44PM +0000, Fuad Tabba wrote: > Hi Joey, > > On Thu, Dec 7, 2023 at 3:00 PM Joey Gouly wrote: > > > > Hello Fuad, > > > > On Wed, Dec 06, 2023 at 10:04:56AM +0000, Fuad Tabba wrote: > > > New trap bits have been defined in the 2023-09 Arm Architecture > > > System Registers xml specification [*]. Moreover, the existing > > > definitions of some of the mask and the RES0 bits overlap, which > > > could be wrong, confusing, or both. > > > > > > Update the bits to represent the latest spec (as of this patch, > > > 2023-09), and ensure that the existing bits are consistent. > > > > > > Subsequent patches will use the generated RES0 fields instead of > > > specifying them manually. This patch keeps the manual encoding of > > > the bits to make it easier to review the series. > > > > > > [*] https://developer.arm.com/downloads/-/exploration-tools > > > > > > Fixes: 0fd76865006d ("KVM: arm64: Add nPIR{E0}_EL1 to HFG traps") > > > Signed-off-by: Fuad Tabba > > > --- > > > arch/arm64/include/asm/kvm_arm.h | 39 ++++++++++++++++++++------------ > > > 1 file changed, 24 insertions(+), 15 deletions(-) > > > > > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > > > index 7de0a7062625..b0dc3249d5cd 100644 > > > --- a/arch/arm64/include/asm/kvm_arm.h > > > +++ b/arch/arm64/include/asm/kvm_arm.h > > > @@ -344,30 +344,39 @@ > > > * Once we get to a point where the two describe the same thing, we'll > > > * merge the definitions. One day. > > > */ > > > -#define __HFGRTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51)) > > > +#define __HFGRTR_EL2_RES0 BIT(51) > > > #define __HFGRTR_EL2_MASK GENMASK(49, 0) > > > -#define __HFGRTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50)) > > > +#define __HFGRTR_EL2_nMASK (GENMASK(63, 52) | BIT(50)) > > > > > > -#define __HFGWTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51) | \ > > > - BIT(46) | BIT(42) | BIT(40) | BIT(28) | \ > > > - GENMASK(26, 25) | BIT(21) | BIT(18) | \ > > > +#define __HFGWTR_EL2_RES0 (BIT(51) | BIT(46) | BIT(42) | BIT(40) | \ > > > + BIT(28) | GENMASK(26, 25) | BIT(21) | BIT(18) | \ > > > GENMASK(15, 14) | GENMASK(10, 9) | BIT(2)) > > > -#define __HFGWTR_EL2_MASK GENMASK(49, 0) > > > -#define __HFGWTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50)) > > > +#define __HFGWTR_EL2_MASK (GENMASK(49, 47) | GENMASK(45, 43) | \ > > > + BIT(41) | GENMASK(39, 29) | BIT(27) | \ > > > + GENMASK(24, 22) | GENMASK(20, 19) | \ > > > + GENMASK(17, 16) | GENMASK(13, 11) | \ > > > + GENMASK(8, 3) | GENMASK(1, 0)) > > > +#define __HFGWTR_EL2_nMASK (GENMASK(63, 52) | BIT(50)) > > > > By adding all these bits to *_nMASK, we're allowing a guest to access registers > > which KVM doesn't (currently) deal with. For example if I apply this patch > > series, a guest can access S2POR_EL1, previously it would print something like: > > > > kvm [80]: Unsupported guest sys_reg access at: ffffc42969c1f270 [600000c5] > > { Op0( 3), Op1( 0), CRn(10), CRm( 2), Op2( 5), func_read }, > > > > After applying this patch series, the guest can read S2POR_EL1. > > > > We don't expose S2POE to the guest through ID_AA64MMFR3_EL1, so a well behaved > > guest shouldn't access it, but there's nothing stopping it. > > > > My question is, is this intended? Or do we need to update the following code > > (and comment!) to trap all the stuff we don't currently handle (along with > > ACCDATA_EL1): > > Thanks for pointing this out, and no, it's not intended. For > consistency, I think it might be good to update the code, as you > suggest, to prevent these accesses. If you and the other reviewers are > happy with that solution I can respin with your suggested fix. I have > a couple of other minor fixes as well for the series. > Thanks for clarifying that. To me it seems weird to use the generated bits directly, and I think that's why the code seems confusing? I think we should stop using __HFGRTR_EL2_nMASK directly in that function, and build it up from '0'. This also matches, I think, with Marc Z wanting to move towards setting these things based on features [1], so maybe something like: u64 r_val = 0; if (cpus_have_final_cap(ARM64_HAS_S1PIE)) r_set |= HFGxTR_EL2_nPIR_EL1 | HFGxTR_EL2_nPIREO_EL1; r_val |= r_set; r_val &= ~r_clr; write_sysreg_s(r_val, SYS_HFGRTR_EL2); That way we just explicitly set which bits we don't want to trap on. We have some weird behaviour right now were we set nSMPRI_EL1 to 1, unless you have FEAT_SME where we set it to 0.. but if you don't have FEAT_SME it's RES0 anyway? The above approach would fix that. Thanks, Joey [1] https://lore.kernel.org/linux-arm-kernel/87bkb285ud.wl-maz@kernel.org/ (last paragraph) > > Cheers, > /fuad > > > > > > static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu) > > { > > > > .. > > > > /* The default is not to trap anything but ACCDATA_EL1 */ > > r_val = __HFGRTR_EL2_nMASK & ~HFGxTR_EL2_nACCDATA_EL1; > > r_val |= r_set; > > r_val &= ~r_clr; > > > > > > Thanks, > > Joey > > > > > > > > -#define __HFGITR_EL2_RES0 GENMASK(63, 57) > > > -#define __HFGITR_EL2_MASK GENMASK(54, 0) > > > -#define __HFGITR_EL2_nMASK GENMASK(56, 55) > > > +#define __HFGITR_EL2_RES0 (BIT(63) | BIT(61)) > > > +#define __HFGITR_EL2_MASK (BIT(62) | BIT(60) | GENMASK(54, 0)) > > > +#define __HFGITR_EL2_nMASK GENMASK(59, 55) > > > > > > #define __HDFGRTR_EL2_RES0 (BIT(49) | BIT(42) | GENMASK(39, 38) | \ > > > GENMASK(21, 20) | BIT(8)) > > > -#define __HDFGRTR_EL2_MASK ~__HDFGRTR_EL2_nMASK > > > +#define __HDFGRTR_EL2_MASK (BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \ > > > + GENMASK(41, 40) | GENMASK(37, 22) | \ > > > + GENMASK(19, 9) | GENMASK(7, 0)) > > > #define __HDFGRTR_EL2_nMASK GENMASK(62, 59) > > > > > > #define __HDFGWTR_EL2_RES0 (BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \ > > > BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \ > > > BIT(22) | BIT(9) | BIT(6)) > > > -#define __HDFGWTR_EL2_MASK ~__HDFGWTR_EL2_nMASK > > > +#define __HDFGWTR_EL2_MASK (GENMASK(57, 52) | GENMASK(50, 48) | \ > > > + GENMASK(46, 44) | GENMASK(42, 41) | \ > > > + GENMASK(37, 35) | GENMASK(33, 31) | \ > > > + GENMASK(29, 23) | GENMASK(21, 10) | \ > > > + GENMASK(8, 7) | GENMASK(5, 0)) > > > #define __HDFGWTR_EL2_nMASK GENMASK(62, 60) > > > > > > #define __HAFGRTR_EL2_RES0 (GENMASK(63, 50) | GENMASK(16, 5)) > > > @@ -375,9 +384,9 @@ > > > #define __HAFGRTR_EL2_nMASK 0UL > > > > > > /* Similar definitions for HCRX_EL2 */ > > > -#define __HCRX_EL2_RES0 (GENMASK(63, 16) | GENMASK(13, 12)) > > > -#define __HCRX_EL2_MASK (0) > > > -#define __HCRX_EL2_nMASK (GENMASK(15, 14) | GENMASK(4, 0)) > > > +#define __HCRX_EL2_RES0 (GENMASK(63, 25) | GENMASK(13, 12)) > > > +#define __HCRX_EL2_MASK (BIT(6)) > > > +#define __HCRX_EL2_nMASK (GENMASK(24, 14) | GENMASK(11, 7) | GENMASK(5, 0)) > > > > > > /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ > > > #define HPFAR_MASK (~UL(0xf)) > > > -- > > > 2.43.0.rc2.451.g8631bc7472-goog > > > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1166DC4167B for ; Thu, 7 Dec 2023 17:13:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Y0qwPRWX3paDmRAAEj0iID1MtABQ2Y4EWGVMvzwMLHE=; b=DDrJOL0wsXVaEm Vd44LLLJLbxa5S2QHo65IMwm8Hnb9nZqo08MYj8ipJWGhpWKwsiWPhmUHnzp/n3buIvOp6aDtBH6H OyBTiwp77sssVYflYcoDFaXMYQcPhrhL94JjBt/r+j0dt+2Yd6/oLi6bkR4riu7XIbGtuwliy15dc P3guW9aG++sAhxAfXMLLOf56tlwQMy578DvRZKSb/J1huRWeG39gAGiUQSJ1Jn/xryPvHXYV1Qdf6 wIAdt/DFNmTxNtyubxaxX1nDf4gokNXaWYNRSum0qSPi0K4wox9OmMZZALhLXuRrSB4GFBwFc42ck SJr3aPTUOK3v+VasXdsQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rBHvf-00DVSK-3D; Thu, 07 Dec 2023 17:12:52 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rBHvc-00DVRv-1i for linux-arm-kernel@lists.infradead.org; Thu, 07 Dec 2023 17:12:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 63C48153B; Thu, 7 Dec 2023 09:13:30 -0800 (PST) Received: from e124191.cambridge.arm.com (e124191.cambridge.arm.com [10.1.197.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E54573F762; Thu, 7 Dec 2023 09:12:42 -0800 (PST) Date: Thu, 7 Dec 2023 17:12:37 +0000 From: Joey Gouly To: Fuad Tabba Cc: kvmarm@lists.linux.dev, maz@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, eric.auger@redhat.com, jingzhangos@google.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 06/12] KVM: arm64: Update and fix FGT register masks Message-ID: <20231207171237.GA87398@e124191.cambridge.arm.com> References: <20231206100503.564090-1-tabba@google.com> <20231206100503.564090-7-tabba@google.com> <20231207150001.GA29745@e124191.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231207_091248_666601_5915C278 X-CRM114-Status: GOOD ( 40.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCBEZWMgMDcsIDIwMjMgYXQgMDM6MDY6NDRQTSArMDAwMCwgRnVhZCBUYWJiYSB3cm90 ZToKPiBIaSBKb2V5LAo+IAo+IE9uIFRodSwgRGVjIDcsIDIwMjMgYXQgMzowMOKAr1BNIEpvZXkg R291bHkgPGpvZXkuZ291bHlAYXJtLmNvbT4gd3JvdGU6Cj4gPgo+ID4gSGVsbG8gRnVhZCwKPiA+ Cj4gPiBPbiBXZWQsIERlYyAwNiwgMjAyMyBhdCAxMDowNDo1NkFNICswMDAwLCBGdWFkIFRhYmJh IHdyb3RlOgo+ID4gPiBOZXcgdHJhcCBiaXRzIGhhdmUgYmVlbiBkZWZpbmVkIGluIHRoZSAyMDIz LTA5IEFybSBBcmNoaXRlY3R1cmUKPiA+ID4gU3lzdGVtIFJlZ2lzdGVycyB4bWwgc3BlY2lmaWNh dGlvbiBbKl0uIE1vcmVvdmVyLCB0aGUgZXhpc3RpbmcKPiA+ID4gZGVmaW5pdGlvbnMgb2Ygc29t ZSBvZiB0aGUgbWFzayBhbmQgdGhlIFJFUzAgYml0cyBvdmVybGFwLCB3aGljaAo+ID4gPiBjb3Vs ZCBiZSB3cm9uZywgY29uZnVzaW5nLCBvciBib3RoLgo+ID4gPgo+ID4gPiBVcGRhdGUgdGhlIGJp dHMgdG8gcmVwcmVzZW50IHRoZSBsYXRlc3Qgc3BlYyAoYXMgb2YgdGhpcyBwYXRjaCwKPiA+ID4g MjAyMy0wOSksIGFuZCBlbnN1cmUgdGhhdCB0aGUgZXhpc3RpbmcgYml0cyBhcmUgY29uc2lzdGVu dC4KPiA+ID4KPiA+ID4gU3Vic2VxdWVudCBwYXRjaGVzIHdpbGwgdXNlIHRoZSBnZW5lcmF0ZWQg UkVTMCBmaWVsZHMgaW5zdGVhZCBvZgo+ID4gPiBzcGVjaWZ5aW5nIHRoZW0gbWFudWFsbHkuIFRo aXMgcGF0Y2gga2VlcHMgdGhlIG1hbnVhbCBlbmNvZGluZyBvZgo+ID4gPiB0aGUgYml0cyB0byBt YWtlIGl0IGVhc2llciB0byByZXZpZXcgdGhlIHNlcmllcy4KPiA+ID4KPiA+ID4gWypdIGh0dHBz Oi8vZGV2ZWxvcGVyLmFybS5jb20vZG93bmxvYWRzLy0vZXhwbG9yYXRpb24tdG9vbHMKPiA+ID4K PiA+ID4gRml4ZXM6IDBmZDc2ODY1MDA2ZCAoIktWTTogYXJtNjQ6IEFkZCBuUElSe0UwfV9FTDEg dG8gSEZHIHRyYXBzIikKPiA+ID4gU2lnbmVkLW9mZi1ieTogRnVhZCBUYWJiYSA8dGFiYmFAZ29v Z2xlLmNvbT4KPiA+ID4gLS0tCj4gPiA+ICBhcmNoL2FybTY0L2luY2x1ZGUvYXNtL2t2bV9hcm0u aCB8IDM5ICsrKysrKysrKysrKysrKysrKysrLS0tLS0tLS0tLS0tCj4gPiA+ICAxIGZpbGUgY2hh bmdlZCwgMjQgaW5zZXJ0aW9ucygrKSwgMTUgZGVsZXRpb25zKC0pCj4gPiA+Cj4gPiA+IGRpZmYg LS1naXQgYS9hcmNoL2FybTY0L2luY2x1ZGUvYXNtL2t2bV9hcm0uaCBiL2FyY2gvYXJtNjQvaW5j bHVkZS9hc20va3ZtX2FybS5oCj4gPiA+IGluZGV4IDdkZTBhNzA2MjYyNS4uYjBkYzMyNDlkNWNk IDEwMDY0NAo+ID4gPiAtLS0gYS9hcmNoL2FybTY0L2luY2x1ZGUvYXNtL2t2bV9hcm0uaAo+ID4g PiArKysgYi9hcmNoL2FybTY0L2luY2x1ZGUvYXNtL2t2bV9hcm0uaAo+ID4gPiBAQCAtMzQ0LDMw ICszNDQsMzkgQEAKPiA+ID4gICAqIE9uY2Ugd2UgZ2V0IHRvIGEgcG9pbnQgd2hlcmUgdGhlIHR3 byBkZXNjcmliZSB0aGUgc2FtZSB0aGluZywgd2UnbGwKPiA+ID4gICAqIG1lcmdlIHRoZSBkZWZp bml0aW9ucy4gT25lIGRheS4KPiA+ID4gICAqLwo+ID4gPiAtI2RlZmluZSBfX0hGR1JUUl9FTDJf UkVTMCAgICAoR0VOTUFTSyg2MywgNTYpIHwgR0VOTUFTSyg1MywgNTEpKQo+ID4gPiArI2RlZmlu ZSBfX0hGR1JUUl9FTDJfUkVTMCAgICBCSVQoNTEpCj4gPiA+ICAjZGVmaW5lIF9fSEZHUlRSX0VM Ml9NQVNLICAgIEdFTk1BU0soNDksIDApCj4gPiA+IC0jZGVmaW5lIF9fSEZHUlRSX0VMMl9uTUFT SyAgIChHRU5NQVNLKDU4LCA1NykgfCBHRU5NQVNLKDU1LCA1NCkgfCBCSVQoNTApKQo+ID4gPiAr I2RlZmluZSBfX0hGR1JUUl9FTDJfbk1BU0sgICAoR0VOTUFTSyg2MywgNTIpIHwgQklUKDUwKSkK PiA+ID4KPiA+ID4gLSNkZWZpbmUgX19IRkdXVFJfRUwyX1JFUzAgICAgKEdFTk1BU0soNjMsIDU2 KSB8IEdFTk1BU0soNTMsIDUxKSB8ICAgIFwKPiA+ID4gLSAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIEJJVCg0NikgfCBCSVQoNDIpIHwgQklUKDQwKSB8IEJJVCgyOCkgfCBcCj4gPiA+IC0g ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBHRU5NQVNLKDI2LCAyNSkgfCBCSVQoMjEpIHwg QklUKDE4KSB8ICBcCj4gPiA+ICsjZGVmaW5lIF9fSEZHV1RSX0VMMl9SRVMwICAgIChCSVQoNTEp IHwgQklUKDQ2KSB8IEJJVCg0MikgfCBCSVQoNDApIHwgXAo+ID4gPiArICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgQklUKDI4KSB8IEdFTk1BU0soMjYsIDI1KSB8IEJJVCgyMSkgfCBCSVQo MTgpIHwgXAo+ID4gPiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgR0VOTUFTSygxNSwg MTQpIHwgR0VOTUFTSygxMCwgOSkgfCBCSVQoMikpCj4gPiA+IC0jZGVmaW5lIF9fSEZHV1RSX0VM Ml9NQVNLICAgIEdFTk1BU0soNDksIDApCj4gPiA+IC0jZGVmaW5lIF9fSEZHV1RSX0VMMl9uTUFT SyAgIChHRU5NQVNLKDU4LCA1NykgfCBHRU5NQVNLKDU1LCA1NCkgfCBCSVQoNTApKQo+ID4gPiAr I2RlZmluZSBfX0hGR1dUUl9FTDJfTUFTSyAgICAoR0VOTUFTSyg0OSwgNDcpIHwgR0VOTUFTSyg0 NSwgNDMpIHwgXAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgQklUKDQxKSB8 IEdFTk1BU0soMzksIDI5KSB8IEJJVCgyNykgfCBcCj4gPiA+ICsgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICBHRU5NQVNLKDI0LCAyMikgfCBHRU5NQVNLKDIwLCAxOSkgfCBcCj4gPiA+ICsg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBHRU5NQVNLKDE3LCAxNikgfCBHRU5NQVNLKDEz LCAxMSkgfCBcCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBHRU5NQVNLKDgs IDMpIHwgR0VOTUFTSygxLCAwKSkKPiA+ID4gKyNkZWZpbmUgX19IRkdXVFJfRUwyX25NQVNLICAg KEdFTk1BU0soNjMsIDUyKSB8IEJJVCg1MCkpCj4gPgo+ID4gQnkgYWRkaW5nIGFsbCB0aGVzZSBi aXRzIHRvICpfbk1BU0ssIHdlJ3JlIGFsbG93aW5nIGEgZ3Vlc3QgdG8gYWNjZXNzIHJlZ2lzdGVy cwo+ID4gd2hpY2ggS1ZNIGRvZXNuJ3QgKGN1cnJlbnRseSkgZGVhbCB3aXRoLiAgRm9yIGV4YW1w bGUgaWYgSSBhcHBseSB0aGlzIHBhdGNoCj4gPiBzZXJpZXMsIGEgZ3Vlc3QgY2FuIGFjY2VzcyBT MlBPUl9FTDEsIHByZXZpb3VzbHkgaXQgd291bGQgcHJpbnQgc29tZXRoaW5nIGxpa2U6Cj4gPgo+ ID4gICAgICAgICBrdm0gWzgwXTogVW5zdXBwb3J0ZWQgZ3Vlc3Qgc3lzX3JlZyBhY2Nlc3MgYXQ6 IGZmZmZjNDI5NjljMWYyNzAgWzYwMDAwMGM1XQo+ID4gICAgICAgICAgeyBPcDAoIDMpLCBPcDEo IDApLCBDUm4oMTApLCBDUm0oIDIpLCBPcDIoIDUpLCBmdW5jX3JlYWQgfSwKPiA+Cj4gPiBBZnRl ciBhcHBseWluZyB0aGlzIHBhdGNoIHNlcmllcywgdGhlIGd1ZXN0IGNhbiByZWFkIFMyUE9SX0VM MS4KPiA+Cj4gPiBXZSBkb24ndCBleHBvc2UgUzJQT0UgdG8gdGhlIGd1ZXN0IHRocm91Z2ggSURf QUE2NE1NRlIzX0VMMSwgc28gYSB3ZWxsIGJlaGF2ZWQKPiA+IGd1ZXN0IHNob3VsZG4ndCBhY2Nl c3MgaXQsIGJ1dCB0aGVyZSdzIG5vdGhpbmcgc3RvcHBpbmcgaXQuCj4gPgo+ID4gTXkgcXVlc3Rp b24gaXMsIGlzIHRoaXMgaW50ZW5kZWQ/IE9yIGRvIHdlIG5lZWQgdG8gdXBkYXRlIHRoZSBmb2xs b3dpbmcgY29kZQo+ID4gKGFuZCBjb21tZW50ISkgdG8gdHJhcCBhbGwgdGhlIHN0dWZmIHdlIGRv bid0IGN1cnJlbnRseSBoYW5kbGUgKGFsb25nIHdpdGgKPiA+IEFDQ0RBVEFfRUwxKToKPiAKPiBU aGFua3MgZm9yIHBvaW50aW5nIHRoaXMgb3V0LCBhbmQgbm8sIGl0J3Mgbm90IGludGVuZGVkLiBG b3IKPiBjb25zaXN0ZW5jeSwgSSB0aGluayBpdCBtaWdodCBiZSBnb29kIHRvIHVwZGF0ZSB0aGUg Y29kZSwgYXMgeW91Cj4gc3VnZ2VzdCwgdG8gcHJldmVudCB0aGVzZSBhY2Nlc3Nlcy4gSWYgeW91 IGFuZCB0aGUgb3RoZXIgcmV2aWV3ZXJzIGFyZQo+IGhhcHB5IHdpdGggdGhhdCBzb2x1dGlvbiBJ IGNhbiByZXNwaW4gd2l0aCB5b3VyIHN1Z2dlc3RlZCBmaXguIEkgaGF2ZQo+IGEgY291cGxlIG9m IG90aGVyIG1pbm9yIGZpeGVzIGFzIHdlbGwgZm9yIHRoZSBzZXJpZXMuCj4gCgpUaGFua3MgZm9y IGNsYXJpZnlpbmcgdGhhdC4KClRvIG1lIGl0IHNlZW1zIHdlaXJkIHRvIHVzZSB0aGUgZ2VuZXJh dGVkIGJpdHMgZGlyZWN0bHksIGFuZCBJIHRoaW5rIHRoYXQncyB3aHkKdGhlIGNvZGUgc2VlbXMg Y29uZnVzaW5nPwoKSSB0aGluayB3ZSBzaG91bGQgc3RvcCB1c2luZyBfX0hGR1JUUl9FTDJfbk1B U0sgZGlyZWN0bHkgaW4gdGhhdCBmdW5jdGlvbiwgYW5kCmJ1aWxkIGl0IHVwIGZyb20gJzAnLiBU aGlzIGFsc28gbWF0Y2hlcywgSSB0aGluaywgd2l0aCBNYXJjIFogd2FudGluZyB0byBtb3ZlCnRv d2FyZHMgc2V0dGluZyB0aGVzZSB0aGluZ3MgYmFzZWQgb24gZmVhdHVyZXMgWzFdLCBzbyBtYXli ZSBzb21ldGhpbmcgbGlrZToKCgl1NjQgcl92YWwgPSAwOwoKCWlmIChjcHVzX2hhdmVfZmluYWxf Y2FwKEFSTTY0X0hBU19TMVBJRSkpCgkJcl9zZXQgfD0gSEZHeFRSX0VMMl9uUElSX0VMMSB8IEhG R3hUUl9FTDJfblBJUkVPX0VMMTsKCglyX3ZhbCB8PSByX3NldDsKCXJfdmFsICY9IH5yX2NscjsK Cgl3cml0ZV9zeXNyZWdfcyhyX3ZhbCwgU1lTX0hGR1JUUl9FTDIpOwoKVGhhdCB3YXkgd2UganVz dCBleHBsaWNpdGx5IHNldCB3aGljaCBiaXRzIHdlIGRvbid0IHdhbnQgdG8gdHJhcCBvbi4gV2Ug aGF2ZQpzb21lIHdlaXJkIGJlaGF2aW91ciByaWdodCBub3cgd2VyZSB3ZSBzZXQgblNNUFJJX0VM MSB0byAxLCB1bmxlc3MgeW91IGhhdmUKRkVBVF9TTUUgd2hlcmUgd2Ugc2V0IGl0IHRvIDAuLiBi dXQgaWYgeW91IGRvbid0IGhhdmUgRkVBVF9TTUUgaXQncyBSRVMwCmFueXdheT8gVGhlIGFib3Zl IGFwcHJvYWNoIHdvdWxkIGZpeCB0aGF0LgoKVGhhbmtzLApKb2V5CgpbMV0gaHR0cHM6Ly9sb3Jl Lmtlcm5lbC5vcmcvbGludXgtYXJtLWtlcm5lbC84N2JrYjI4NXVkLndsLW1hekBrZXJuZWwub3Jn LyAobGFzdCBwYXJhZ3JhcGgpCgo+IAo+IENoZWVycywKPiAvZnVhZAo+IAo+IAo+ID4KPiA+ICAg ICAgICAgc3RhdGljIGlubGluZSB2b2lkIF9fYWN0aXZhdGVfdHJhcHNfaGZneHRyKHN0cnVjdCBr dm1fdmNwdSAqdmNwdSkKPiA+ICAgICAgICAgewo+ID4KPiA+ICAgICAgICAgICAgICAgICAuLgo+ ID4KPiA+ICAgICAgICAgICAgICAgICAvKiBUaGUgZGVmYXVsdCBpcyBub3QgdG8gdHJhcCBhbnl0 aGluZyBidXQgQUNDREFUQV9FTDEgKi8KPiA+ICAgICAgICAgICAgICAgICByX3ZhbCA9IF9fSEZH UlRSX0VMMl9uTUFTSyAmIH5IRkd4VFJfRUwyX25BQ0NEQVRBX0VMMTsKPiA+ICAgICAgICAgICAg ICAgICByX3ZhbCB8PSByX3NldDsKPiA+ICAgICAgICAgICAgICAgICByX3ZhbCAmPSB+cl9jbHI7 Cj4gPgo+ID4KPiA+IFRoYW5rcywKPiA+IEpvZXkKPiA+Cj4gPiA+Cj4gPiA+IC0jZGVmaW5lIF9f SEZHSVRSX0VMMl9SRVMwICAgIEdFTk1BU0soNjMsIDU3KQo+ID4gPiAtI2RlZmluZSBfX0hGR0lU Ul9FTDJfTUFTSyAgICBHRU5NQVNLKDU0LCAwKQo+ID4gPiAtI2RlZmluZSBfX0hGR0lUUl9FTDJf bk1BU0sgICBHRU5NQVNLKDU2LCA1NSkKPiA+ID4gKyNkZWZpbmUgX19IRkdJVFJfRUwyX1JFUzAg ICAgKEJJVCg2MykgfCBCSVQoNjEpKQo+ID4gPiArI2RlZmluZSBfX0hGR0lUUl9FTDJfTUFTSyAg ICAoQklUKDYyKSB8IEJJVCg2MCkgfCBHRU5NQVNLKDU0LCAwKSkKPiA+ID4gKyNkZWZpbmUgX19I RkdJVFJfRUwyX25NQVNLICAgR0VOTUFTSyg1OSwgNTUpCj4gPiA+Cj4gPiA+ICAjZGVmaW5lIF9f SERGR1JUUl9FTDJfUkVTMCAgIChCSVQoNDkpIHwgQklUKDQyKSB8IEdFTk1BU0soMzksIDM4KSB8 ICBcCj4gPiA+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBHRU5NQVNLKDIxLCAyMCkg fCBCSVQoOCkpCj4gPiA+IC0jZGVmaW5lIF9fSERGR1JUUl9FTDJfTUFTSyAgIH5fX0hERkdSVFJf RUwyX25NQVNLCj4gPiA+ICsjZGVmaW5lIF9fSERGR1JUUl9FTDJfTUFTSyAgIChCSVQoNjMpIHwg R0VOTUFTSyg1OCwgNTApIHwgR0VOTUFTSyg0OCwgNDMpIHwgXAo+ID4gPiArICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgR0VOTUFTSyg0MSwgNDApIHwgR0VOTUFTSygzNywgMjIpIHwgXAo+ ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgR0VOTUFTSygxOSwgOSkgfCBHRU5N QVNLKDcsIDApKQo+ID4gPiAgI2RlZmluZSBfX0hERkdSVFJfRUwyX25NQVNLICBHRU5NQVNLKDYy LCA1OSkKPiA+ID4KPiA+ID4gICNkZWZpbmUgX19IREZHV1RSX0VMMl9SRVMwICAgKEJJVCg2Mykg fCBHRU5NQVNLKDU5LCA1OCkgfCBCSVQoNTEpIHwgQklUKDQ3KSB8IFwKPiA+ID4gICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIEJJVCg0MykgfCBHRU5NQVNLKDQwLCAzOCkgfCBCSVQoMzQp IHwgQklUKDMwKSB8IFwKPiA+ID4gICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIEJJVCgy MikgfCBCSVQoOSkgfCBCSVQoNikpCj4gPiA+IC0jZGVmaW5lIF9fSERGR1dUUl9FTDJfTUFTSyAg IH5fX0hERkdXVFJfRUwyX25NQVNLCj4gPiA+ICsjZGVmaW5lIF9fSERGR1dUUl9FTDJfTUFTSyAg IChHRU5NQVNLKDU3LCA1MikgfCBHRU5NQVNLKDUwLCA0OCkgfCBcCj4gPiA+ICsgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICBHRU5NQVNLKDQ2LCA0NCkgfCBHRU5NQVNLKDQyLCA0MSkgfCBc Cj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBHRU5NQVNLKDM3LCAzNSkgfCBH RU5NQVNLKDMzLCAzMSkgfCBcCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBH RU5NQVNLKDI5LCAyMykgfCBHRU5NQVNLKDIxLCAxMCkgfCBcCj4gPiA+ICsgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICBHRU5NQVNLKDgsIDcpIHwgR0VOTUFTSyg1LCAwKSkKPiA+ID4gICNk ZWZpbmUgX19IREZHV1RSX0VMMl9uTUFTSyAgR0VOTUFTSyg2MiwgNjApCj4gPiA+Cj4gPiA+ICAj ZGVmaW5lIF9fSEFGR1JUUl9FTDJfUkVTMCAgIChHRU5NQVNLKDYzLCA1MCkgfCBHRU5NQVNLKDE2 LCA1KSkKPiA+ID4gQEAgLTM3NSw5ICszODQsOSBAQAo+ID4gPiAgI2RlZmluZSBfX0hBRkdSVFJf RUwyX25NQVNLICAwVUwKPiA+ID4KPiA+ID4gIC8qIFNpbWlsYXIgZGVmaW5pdGlvbnMgZm9yIEhD UlhfRUwyICovCj4gPiA+IC0jZGVmaW5lIF9fSENSWF9FTDJfUkVTMCAgICAgICAgICAgICAgKEdF Tk1BU0soNjMsIDE2KSB8IEdFTk1BU0soMTMsIDEyKSkKPiA+ID4gLSNkZWZpbmUgX19IQ1JYX0VM Ml9NQVNLICAgICAgICAgICAgICAoMCkKPiA+ID4gLSNkZWZpbmUgX19IQ1JYX0VMMl9uTUFTSyAg ICAgKEdFTk1BU0soMTUsIDE0KSB8IEdFTk1BU0soNCwgMCkpCj4gPiA+ICsjZGVmaW5lIF9fSENS WF9FTDJfUkVTMCAgICAgICAgIChHRU5NQVNLKDYzLCAyNSkgfCBHRU5NQVNLKDEzLCAxMikpCj4g PiA+ICsjZGVmaW5lIF9fSENSWF9FTDJfTUFTSyAgICAgICAgICAgICAgKEJJVCg2KSkKPiA+ID4g KyNkZWZpbmUgX19IQ1JYX0VMMl9uTUFTSyAgICAgKEdFTk1BU0soMjQsIDE0KSB8IEdFTk1BU0so MTEsIDcpIHwgR0VOTUFTSyg1LCAwKSkKPiA+ID4KPiA+ID4gIC8qIEh5cCBQcmVmZXRjaCBGYXVs dCBBZGRyZXNzIFJlZ2lzdGVyIChIUEZBUi9IREZBUikgKi8KPiA+ID4gICNkZWZpbmUgSFBGQVJf TUFTSyAgICh+VUwoMHhmKSkKPiA+ID4gLS0KPiA+ID4gMi40My4wLnJjMi40NTEuZzg2MzFiYzc0 NzItZ29vZwo+ID4gPgo+ID4gPgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5l bEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4v bGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=