From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: David <david@ixit.cz>
Cc: krzysztof.kozlowski@linaro.org, agross@kernel.org,
andersson@kernel.org, bhelgaas@google.com, conor+dt@kernel.org,
conor.dooley@microchip.com, devicetree@vger.kernel.org,
konrad.dybcio@linaro.org, krzysztof.kozlowski+dt@linaro.org,
kw@linux.com, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
lpieralisi@kernel.org, mani@kernel.org, robh@kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: adjust iommu-map for different SoC
Date: Fri, 29 Dec 2023 22:47:54 +0530 [thread overview]
Message-ID: <20231229171754.GD9098@thinkpad> (raw)
In-Reply-To: <dfc4f26c-74fe-47b3-af96-e97765082f4e@ixit.cz>
On Fri, Dec 29, 2023 at 04:36:31PM +0100, David wrote:
> > + minItems: 1
> Hello Krzysztof,
>
> the driver will accept 0 just fine, so I think this definition may be wrong.
>
It's not entirely wrong but the actual SID mapping differs between SoCs.
> I sent just generic "dt-bindings: PCI: qcom: delimit number of iommu-map entries" which doesn't care about the numbers (in similar fashion as other bindings having iommu-map).
>
No, we should not just ignore the MAX limit. If you add <N> number of entries
exceeding the max SID assigned to PCIe bus, it will fail.
- Mani
> Tell me what you think.
>
> David
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2023-12-29 17:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-20 7:09 [PATCH v2 1/2] dt-bindings: PCI: qcom: adjust iommu-map for different SoC Krzysztof Kozlowski
2023-11-20 7:09 ` [PATCH v2 2/2] dt-bindings: PCI: qcom: correct clocks for SC8180x and SM8150 Krzysztof Kozlowski
2023-11-20 10:11 ` Dmitry Baryshkov
2023-11-20 10:48 ` Krzysztof Kozlowski
2023-11-21 6:54 ` Manivannan Sadhasivam
2023-12-29 15:36 ` [PATCH v2 1/2] dt-bindings: PCI: qcom: adjust iommu-map for different SoC David
2023-12-29 17:17 ` Manivannan Sadhasivam [this message]
2023-12-29 17:59 ` David Heidelberg
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