mxs: enable phy-clock in the driver?

[LW@KARO-electronics.de (Lothar Waßmann)]

Hi,

Shawn Guo writes:
> On Sun, Jan 08, 2012 at 03:45:58PM +0100, Wolfram Sang wrote:
> > Hi Shawn,
> > 
> > I recently noticed that my tx28 board did not have net when booting from NAND
> > (before that, barebox was setting up the network). Adding lines like these from
> > mx28evk helped:
> > 
> > 228         /* Enable fec phy clock */
> > 229         clk = clk_get_sys("pll2", NULL);
> > 230         if (!IS_ERR(clk))
> > 231                 clk_enable(clk);
> > 
> > So, if every board seems to need this, I'd think this should rather be in the
> > driver? Am I correct or is there something I have overlooked?
> > 
> Hmm, as far as I know, at least m28evk from denx does not need this.
> Different from that imx28 supplies clock to phy on mx28evk board,
> m28evk has phy supply clock to imx28. 
> 
The TX28 derives its PHY clock from the ENET_CLK pin of the
processor. Thus the CLK_ENET_TIME should be enabled by the driver as
mentioned in <20120108033238.GA19721@S2101-09.ap.freescale.net>


Lothar Wa?mann
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