[RFC 1/9] arm64: dts: qcom: sm8250: describe the PCIe port

From: Bartosz Golaszewski <brgl@bgdev.pl>
To: "Kalle Valo" <kvalo@kernel.org>,
	"David S . Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konrad.dybcio@linaro.org>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Chris Morgan" <macromorgan@hotmail.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	"Arnd Bergmann" <arnd@arndb.de>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Nícolas F . R . A . Prado" <nfraprado@collabora.com>,
	"Marek Szyprowski" <m.szyprowski@samsung.com>,
	"Peng Fan" <peng.fan@nxp.com>,
	"Robert Richter" <rrichter@amd.com>,
	"Dan Williams" <dan.j.williams@intel.com>,
	"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
	"Terry Bowman" <terry.bowman@amd.com>,
	"Kuppuswamy Sathyanarayanan"
	<sathyanarayanan.kuppuswamy@linux.intel.com>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Alex Elder" <elder@linaro.org>,
	"Srini Kandagatla" <srinivas.kandagatla@linaro.org>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>
Cc: linux-wireless@vger.kernel.org, netdev@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
	Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Subject: [RFC 1/9] arm64: dts: qcom: sm8250: describe the PCIe port
Date: Thu,  4 Jan 2024 14:01:15 +0100	[thread overview]
Message-ID: <20240104130123.37115-2-brgl@bgdev.pl> (raw)
In-Reply-To: <20240104130123.37115-1-brgl@bgdev.pl>

From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>

Improve the description of the PCIe topology by defining the port node
at the SoC level.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 760501c1301a..fef9c314ce55 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2197,6 +2197,16 @@ pcie0: pcie@1c00000 {
 			dma-coherent;
 
 			status = "disabled";
+
+			pcieport0: pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+
+				bus-range = <0x01 0xff>;
+			};
 		};
 
 		pcie0_phy: phy@1c06000 {
-- 
2.40.1

