From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
<alison.schofield@intel.com>, <dave@stgolabs.net>
Subject: Re: [PATCH v14 19/19] cxl: Check qos_class validity on memdev probe
Date: Mon, 8 Jan 2024 14:01:42 +0000 [thread overview]
Message-ID: <20240108140142.0000415c@Huawei.com> (raw)
In-Reply-To: <2fb48806-ae84-4e6e-82aa-712b4e511142@intel.com>
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int cxl_qos_match(struct cxl_port *root_port,
> >> + struct list_head *work_list,
> >> + struct list_head *discard_list)
> >> +{
> >> + struct cxl_dpa_perf *dpa_perf, *n;
> >> + struct qos_class_ctx ctx;
> >> + int rc;
> >> +
> >> + if (list_empty(work_list))
> >> + return 0;
> >> +
> >> + list_for_each_entry_safe(dpa_perf, n, work_list, list) {
> >> + ctx = (struct qos_class_ctx) {
> >> + .matched = false,
> >> + .dev_qos_class = dpa_perf->qos_class,
> >> + };
> >
> > as above the dev_qos_class doesn't change so can we not
> > reject it early here?
> > if (!dpa_perf->qos_class)
> > continue; /* I think? */
>
> Not sure what you mean here. qos_class can be 0.
oops. Invalid was I think my intent though who knows. That was last year!
prev parent reply other threads:[~2024-01-08 14:01 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-13 16:41 [PATCH v14 00/19] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-12-13 16:41 ` [PATCH v14 01/19] lib/firmware_table: tables: Add CDAT table parsing support Dave Jiang
2023-12-13 16:41 ` [PATCH v14 02/19] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' Dave Jiang
2023-12-13 16:41 ` [PATCH v14 03/19] acpi: numa: Create enum for memory_target access coordinates indexing Dave Jiang
2023-12-13 16:41 ` [PATCH v14 04/19] acpi: numa: Add genport target allocation to the HMAT parsing Dave Jiang
2023-12-13 16:41 ` [PATCH v14 05/19] acpi: Break out nesting for hmat_parse_locality() Dave Jiang
2023-12-13 16:41 ` [PATCH v14 06/19] acpi: numa: Add setting of generic port system locality attributes Dave Jiang
2023-12-13 16:42 ` [PATCH v14 07/19] acpi: numa: Add helper function to retrieve the performance attributes Dave Jiang
2023-12-13 16:42 ` [PATCH v14 08/19] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-12-13 16:42 ` [PATCH v14 09/19] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-12-13 16:42 ` [PATCH v14 10/19] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-12-13 16:42 ` [PATCH v14 11/19] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-12-13 16:42 ` [PATCH v14 12/19] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-12-13 16:42 ` [PATCH v14 13/19] tools/testing/cxl: Add hostbridge UID string for cxl_test mock hb devices Dave Jiang
2023-12-13 16:42 ` [PATCH v14 14/19] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-12-13 16:42 ` [PATCH v14 15/19] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-12-13 16:42 ` [PATCH v14 16/19] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-12-13 16:43 ` [PATCH v14 17/19] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-12-13 16:43 ` [PATCH v14 18/19] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-12-15 20:33 ` Dave Jiang
2023-12-18 16:28 ` Dave Jiang
2023-12-13 16:43 ` [PATCH v14 19/19] cxl: Check qos_class validity on memdev probe Dave Jiang
2023-12-19 16:42 ` Jonathan Cameron
2023-12-20 22:26 ` Dave Jiang
2024-01-08 14:01 ` Jonathan Cameron [this message]
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