From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CBB91B952; Mon, 15 Jan 2024 23:28:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qNMYPzU2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 15811C433C7; Mon, 15 Jan 2024 23:28:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1705361305; bh=nRA6/zOt2XFjcIKDedy6Jy81KL9baOfv490eNKYrqFM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qNMYPzU2ni+n2XLPMwRXlFrs7Vho/KTl28Mmp3oC7suohWiHaWoIXyVXiIhPK30ur i0I2hI3pXOJUix9rACFHcV1VvLMuIeqK82VvX0iyZtOJwPWunpcyiZk0GiRZlyJ3go QAi7DhIIPdzkBwN8YsXasPqMvrjcQkmDc81tpXFOhtrpK6n7e/qDZE7tAmeIKDF04d N7SaWmf8US2xbothP7lmqBuoB4DrcRIoKmA+WMWriBf5IYe1sQ7X7z9GtujC3leXaQ jELarg0KmV4FsPyRcdMQQmN8c0ASMHCHVmD+cksr1fi6Fg3XKTtCUh0F7TuFXju9F3 caxikNfLzs7Hw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Mark Rutland , Will Deacon , Sasha Levin , peterz@infradead.org, mingo@redhat.com, acme@kernel.org, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Subject: [PATCH AUTOSEL 5.10 03/10] drivers/perf: pmuv3: don't expose SW_INCR event in sysfs Date: Mon, 15 Jan 2024 18:27:52 -0500 Message-ID: <20240115232818.210010-3-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240115232818.210010-1-sashal@kernel.org> References: <20240115232818.210010-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 5.10.208 Content-Transfer-Encoding: 8bit From: Mark Rutland [ Upstream commit ca6f537e459e2da4b331fe8928d1a0b0f9301f42 ] The SW_INCR event is somewhat unusual, and depends on the specific HW counter that it is programmed into. When programmed into PMEVCNTR, SW_INCR will count any writes to PMSWINC_EL0 with bit n set, ignoring writes to SW_INCR with bit n clear. Event rotation means that there's no fixed relationship between perf_events and HW counters, so this isn't all that useful. Further, we program PMUSERENR.{SW,EN}=={0,0}, which causes EL0 writes to PMSWINC_EL0 to be trapped and handled as UNDEFINED, resulting in a SIGILL to userspace. Given that, it's not a good idea to expose SW_INCR in sysfs. Hide it as we did for CHAIN back in commit: 4ba2578fa7b55701 ("arm64: perf: don't expose CHAIN event in sysfs") Signed-off-by: Mark Rutland Cc: Will Deacon Link: https://lore.kernel.org/r/20231204115847.2993026-1-mark.rutland@arm.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- arch/arm64/kernel/perf_event.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index cdb3d4549b3a..8e428f8dd108 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -171,7 +171,11 @@ armv8pmu_events_sysfs_show(struct device *dev, }).attr.attr) static struct attribute *armv8_pmuv3_event_attrs[] = { - ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR), + /* + * Don't expose the sw_incr event in /sys. It's not usable as writes to + * PMSWINC_EL0 will trap as PMUSERENR.{SW,EN}=={0,0} and event rotation + * means we don't have a fixed event<->counter relationship regardless. + */ ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL), ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL), ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL), -- 2.43.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76477C3DA79 for ; Mon, 15 Jan 2024 23:28:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qhcUtKEISMyR7SikA21ycR+YgvtIg5cMwkyhFs6jfqA=; b=Ftw23Enz1iBdac 152QNOV992nc7UNjwjM4TKPCBOmwpTIMLo5ZLBBFTo0wtkDrynDiKuf1tXwMyoOiRpE3hUU1aiibE fsmYw6xgjmAkWeBsUkQLjdHVwXY+UONK3bDRrNTlX1cw+ZLViySDTBaOYAixr3V0vx0Gerr4DfVwg lNqxenbu+gnKI0Jz6dNijXaL8QRas8xkmfOKTCi2VRU0oKv6AdoklQc+ZI/MXQ0R45Y/CyVjVgLls VmTpEthz1ejq4XCeQPdRspPE1onJCUiz2rlgN4VH0kQk2F4QYGTcldPZk956AFND9xdNKoJzfRfbT UoCzdWKBGsTTAbiZZn2g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rPWNZ-00AMuN-1w; Mon, 15 Jan 2024 23:28:29 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rPWNX-00AMsw-0P for linux-arm-kernel@lists.infradead.org; Mon, 15 Jan 2024 23:28:28 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id CF430B80D55; Mon, 15 Jan 2024 23:28:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 15811C433C7; Mon, 15 Jan 2024 23:28:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1705361305; bh=nRA6/zOt2XFjcIKDedy6Jy81KL9baOfv490eNKYrqFM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qNMYPzU2ni+n2XLPMwRXlFrs7Vho/KTl28Mmp3oC7suohWiHaWoIXyVXiIhPK30ur i0I2hI3pXOJUix9rACFHcV1VvLMuIeqK82VvX0iyZtOJwPWunpcyiZk0GiRZlyJ3go QAi7DhIIPdzkBwN8YsXasPqMvrjcQkmDc81tpXFOhtrpK6n7e/qDZE7tAmeIKDF04d N7SaWmf8US2xbothP7lmqBuoB4DrcRIoKmA+WMWriBf5IYe1sQ7X7z9GtujC3leXaQ jELarg0KmV4FsPyRcdMQQmN8c0ASMHCHVmD+cksr1fi6Fg3XKTtCUh0F7TuFXju9F3 caxikNfLzs7Hw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Mark Rutland , Will Deacon , Sasha Levin , peterz@infradead.org, mingo@redhat.com, acme@kernel.org, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Subject: [PATCH AUTOSEL 5.10 03/10] drivers/perf: pmuv3: don't expose SW_INCR event in sysfs Date: Mon, 15 Jan 2024 18:27:52 -0500 Message-ID: <20240115232818.210010-3-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240115232818.210010-1-sashal@kernel.org> References: <20240115232818.210010-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 5.10.208 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240115_152827_317427_61465FEC X-CRM114-Status: GOOD ( 11.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Rutland [ Upstream commit ca6f537e459e2da4b331fe8928d1a0b0f9301f42 ] The SW_INCR event is somewhat unusual, and depends on the specific HW counter that it is programmed into. When programmed into PMEVCNTR, SW_INCR will count any writes to PMSWINC_EL0 with bit n set, ignoring writes to SW_INCR with bit n clear. Event rotation means that there's no fixed relationship between perf_events and HW counters, so this isn't all that useful. Further, we program PMUSERENR.{SW,EN}=={0,0}, which causes EL0 writes to PMSWINC_EL0 to be trapped and handled as UNDEFINED, resulting in a SIGILL to userspace. Given that, it's not a good idea to expose SW_INCR in sysfs. Hide it as we did for CHAIN back in commit: 4ba2578fa7b55701 ("arm64: perf: don't expose CHAIN event in sysfs") Signed-off-by: Mark Rutland Cc: Will Deacon Link: https://lore.kernel.org/r/20231204115847.2993026-1-mark.rutland@arm.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- arch/arm64/kernel/perf_event.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index cdb3d4549b3a..8e428f8dd108 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -171,7 +171,11 @@ armv8pmu_events_sysfs_show(struct device *dev, }).attr.attr) static struct attribute *armv8_pmuv3_event_attrs[] = { - ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR), + /* + * Don't expose the sw_incr event in /sys. It's not usable as writes to + * PMSWINC_EL0 will trap as PMUSERENR.{SW,EN}=={0,0} and event rotation + * means we don't have a fixed event<->counter relationship regardless. + */ ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL), ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL), ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL), -- 2.43.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel