From: Steven Rostedt <rostedt@goodmis.org>
To: Matthieu Baerts <matttbe@kernel.org>
Cc: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Peter Zijlstra <peterz@infradead.org>,
linux-kernel@vger.kernel.org,
Huacai Chen <chenhuacai@loongson.cn>,
Jinyang He <hejinyang@loongson.cn>,
Tiezhu Yang <yangtiezhu@loongson.cn>,
"Naveen N . Rao" <naveen.n.rao@linux.ibm.com>
Subject: Re: [PATCH -tip v2] x86/kprobes: Drop removed INT3 handling code
Date: Sun, 21 Jan 2024 10:33:23 -0500 [thread overview]
Message-ID: <20240121103323.6a48d0fb@rorschach.local.home> (raw)
In-Reply-To: <20240121103144.4bf735c6@rorschach.local.home>
On Sun, 21 Jan 2024 10:31:44 -0500
Steven Rostedt <rostedt@goodmis.org> wrote:
> My guess is that qemu does not treat the IPI being sent as a memory
> barrier, and then the CPUs do not see a consistent memory view after
> the IPIs are sent. That's a bug in qemu!
More specifically, I bet qemu may be doing a dcache barrier, but not an
icache barrier in the interrupt. If the code is already in qemu's
pipeline, it may not be flushing it like real hardware would do.
-- Steve
next prev parent reply other threads:[~2024-01-21 15:33 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-30 13:33 [PATCH -tip v2] x86/kprobes: Drop removed INT3 handling code Masami Hiramatsu (Google)
2023-01-07 11:36 ` [tip: perf/core] " tip-bot2 for Masami Hiramatsu (Google)
2024-01-20 17:44 ` [PATCH -tip v2] " Matthieu Baerts
2024-01-20 22:05 ` Steven Rostedt
2024-01-21 2:28 ` Masami Hiramatsu
2024-01-21 9:05 ` Masami Hiramatsu
2024-01-21 15:23 ` Matthieu Baerts
2024-01-21 15:31 ` Steven Rostedt
2024-01-21 15:33 ` Steven Rostedt [this message]
2024-01-21 16:20 ` Matthieu Baerts
2024-01-21 21:59 ` Matthieu Baerts
2024-01-22 1:17 ` Masami Hiramatsu
2024-01-21 15:42 ` Steven Rostedt
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