From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AD2474E09; Tue, 23 Jan 2024 02:04:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705975471; cv=none; b=CfoQFK2mSnPgWNJGLGqiQdA53gurJnv9f4nV6kejtbb8oK8N29gORLudX5zkuri34DcixJO3M8+c1/LwadbJxupyyUTGXYkjWQBGiYujTjELsU5RWniFF1QvPKlKzPyIabQNTSnlgYF4E0LUOlrWVDZCAEksInlZcmXqsb+ddls= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705975471; c=relaxed/simple; bh=bMWW2DmhEYyGVJkOBcvo9GPnHkpUEPmXT8kujwoCrSo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Yb4FcaSA7lMAUbyUXrzUQ4T6BFRSOhq9OZoD5tCsZqJIfFbezznxHxUaBNK9kBtEX7P6h0+B6ym4Q62pL11fdOimdkufZ9lNeDdDGbMpyL+09nAspOvuBnyULCqaAuOUmTzjhRWgC7L4JJVsnoInSZRUp8qrFaOvh8d15MWqRlg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=F5NL5niW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="F5NL5niW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00CC9C433C7; Tue, 23 Jan 2024 02:04:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1705975471; bh=bMWW2DmhEYyGVJkOBcvo9GPnHkpUEPmXT8kujwoCrSo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F5NL5niWD/L6a/93/IyhmpsjExwsK9MiaJcPlJD+YihpaPvVAnzv3OtXEO2IeCGP8 QOj0WlsRMlOeHQgwWYFmsGP4wAVxOVpXD3yn1A5Af7+6CV0HGUS4MFa9BkLUJx7GbA Bh/ZWOhD2szxyM4q2vp33TnJU+ZaUcfbVLnJOjUU= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, qizhong cheng , Jianjun Wang , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , AngeloGioacchino Del Regno Subject: [PATCH 6.6 426/583] PCI: mediatek: Clear interrupt status before dispatching handler Date: Mon, 22 Jan 2024 15:57:57 -0800 Message-ID: <20240122235825.021362605@linuxfoundation.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122235812.238724226@linuxfoundation.org> References: <20240122235812.238724226@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: qizhong cheng commit 4e11c29873a8a296a20f99b3e03095e65ebf897d upstream. We found a failure when using the iperf tool during WiFi performance testing, where some MSIs were received while clearing the interrupt status, and these MSIs cannot be serviced. The interrupt status can be cleared even if the MSI status remains pending. As such, given the edge-triggered interrupt type, its status should be cleared before being dispatched to the handler of the underling device. [kwilczynski: commit log, code comment wording] Link: https://lore.kernel.org/linux-pci/20231211094923.31967-1-jianjun.wang@mediatek.com Fixes: 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622") Signed-off-by: qizhong cheng Signed-off-by: Jianjun Wang Signed-off-by: Krzysztof Wilczyński [bhelgaas: rewrap comment] Signed-off-by: Bjorn Helgaas Reviewed-by: AngeloGioacchino Del Regno Cc: Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/pcie-mediatek.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -617,12 +617,18 @@ static void mtk_pcie_intr_handler(struct if (status & MSI_STATUS){ unsigned long imsi_status; + /* + * The interrupt status can be cleared even if the + * MSI status remains pending. As such, given the + * edge-triggered interrupt type, its status should + * be cleared before being dispatched to the + * handler of the underlying device. + */ + writel(MSI_STATUS, port->base + PCIE_INT_STATUS); while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) generic_handle_domain_irq(port->inner_domain, bit); } - /* Clear MSI interrupt status */ - writel(MSI_STATUS, port->base + PCIE_INT_STATUS); } }