From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79D601353F6; Tue, 23 Jan 2024 00:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705969636; cv=none; b=gXA0s9yhRrqTLfkr1NeKv96Emut1z/gMPTZ5qvf1qOcfYgdHSjKkQ7G+0Z4VrPbLTdRVnavJUe6MvFuC3lvcwBGlFEbzr8BmSGISb745iCV71vijXl2xmmItmw7974icdR/w7tMByeogF6tWWBzktPSC/iqn5ubvjR7pVqoy188= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705969636; c=relaxed/simple; bh=JvTul+SWomYj7T6vkGzYGi6S1HD/rkUVsXCGPPs+2EE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W+9zLkO6uHfGU1s7qmSyHFT07MCjub1JNkOlObdP2AGL1DHf7lA0EWctz6c/leEV4QqR+uxStwkCkBmvnLhjz00xsFQlCat399vI+86EebvJMlDvLp4r5j6KXz35aa2iQxEL7uuGfc/t+3cxKerNMAjVlHBk3pVwWnjEvw2Y4Vc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=m+zcSr5I; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="m+zcSr5I" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3DE49C43399; Tue, 23 Jan 2024 00:27:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1705969636; bh=JvTul+SWomYj7T6vkGzYGi6S1HD/rkUVsXCGPPs+2EE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m+zcSr5INLQg9Z0x75LsDrYiwTlDBfj0NgO2lxVxUfO/PfzpRKCWfl+MXvH1jAVdn VVjkhrav/nHeDvf3IFDfzb7oSLkdK+CtXftRS7sCnMDdPs8qYUSBncsCKNP15fCy8m OAVOCgzHl8WP3xgaQ3nPFV9/mVFBXELRgE/+nQy4= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Konrad Dybcio , Bjorn Andersson , Sasha Levin Subject: [PATCH 6.7 349/641] clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs Date: Mon, 22 Jan 2024 15:54:13 -0800 Message-ID: <20240122235828.842953465@linuxfoundation.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122235818.091081209@linuxfoundation.org> References: <20240122235818.091081209@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.7-stable review patch. If anyone has any objections, please let me know. ------------------ From: Konrad Dybcio [ Upstream commit 7e77a39265293ea4f05e20fff180755503c49918 ] The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Following other recent Qualcomm platforms, describe this register and the corresponding mask for the PCIe (and _phy) GDSCs. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-5-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- drivers/clk/qcom/gcc-sm8550.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index a16d07426b71..73bda0d03aa7 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -2998,6 +2998,8 @@ static struct clk_branch gcc_video_axi1_clk = { static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, + .collapse_ctrl = 0x52020, + .collapse_mask = BIT(0), .pd = { .name = "pcie_0_gdsc", }, @@ -3007,6 +3009,8 @@ static struct gdsc pcie_0_gdsc = { static struct gdsc pcie_0_phy_gdsc = { .gdscr = 0x6c000, + .collapse_ctrl = 0x52020, + .collapse_mask = BIT(3), .pd = { .name = "pcie_0_phy_gdsc", }, @@ -3016,6 +3020,8 @@ static struct gdsc pcie_0_phy_gdsc = { static struct gdsc pcie_1_gdsc = { .gdscr = 0x8d004, + .collapse_ctrl = 0x52020, + .collapse_mask = BIT(1), .pd = { .name = "pcie_1_gdsc", }, @@ -3025,6 +3031,8 @@ static struct gdsc pcie_1_gdsc = { static struct gdsc pcie_1_phy_gdsc = { .gdscr = 0x8e000, + .collapse_ctrl = 0x52020, + .collapse_mask = BIT(4), .pd = { .name = "pcie_1_phy_gdsc", }, -- 2.43.0