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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id b26-20020a056402139a00b0055c4c97b1f2sm591166edv.91.2024.01.26.05.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 05:31:04 -0800 (PST) From: Andrew Jones To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, dbarboza@ventanamicro.com Subject: [PATCH v2 1/6] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() Date: Fri, 26 Jan 2024 14:31:03 +0100 Message-ID: <20240126133101.61344-9-ajones@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240126133101.61344-8-ajones@ventanamicro.com> References: <20240126133101.61344-8-ajones@ventanamicro.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza Recent changes in options handling removed the 'mmu' default the bare CPUs had, meaning that we must enable 'mmu' by hand when using the rva22s64 profile CPU. Given that this profile is setting a satp mode, it already implies that we need a 'mmu'. Enable the 'mmu' in this case. Signed-off-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index da437975b429..88f92d1c7d2c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1107,6 +1107,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, #ifndef CONFIG_USER_ONLY if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { + object_property_set_bool(obj, "mmu", true, NULL); const char *satp_prop = satp_mode_str(profile->satp_mode, riscv_cpu_is_32bit(cpu)); object_property_set_bool(obj, satp_prop, profile->enabled, NULL); -- 2.43.0