From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8F6A200AC for ; Sat, 27 Jan 2024 23:18:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706397539; cv=none; b=bojrCrsqNtJs3hGPMkiFTt2vkZkbtgPCYbApjRx/wDGz9aTtNkH/h6BI/LhqLGtMBU8P7g/nIAXm2FFix4oveUUBDjIUEpanoiqe19HGhbQ2NMejm4crxSjACGOhgqIm83kFVotMWOZGbNuAkZzw73MWLk2u31oImqGrcz81mow= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706397539; c=relaxed/simple; bh=nLv/Lkbz0ZvggWXuZdhZ6HHw2ZS5D46LumQ7ZmgJFR8=; h=Subject:To:Cc:From:Date:Message-ID:MIME-Version:Content-Type; b=qV7XGjCVgAF9iWqqlQ45YqplkJyS0ZYTtI1LWhZ8yHIWiygLoT3RO7E/is9ux1Ve94wAbI5kpXiWW1wUmp+An5uVYjvrzffT21hwqCyKs7v/e+P0Q4LBwn2wmfVdFlRD5Gtx/7IdSk+WS3ds2uOdgkrf0vhMNFl2iWm41A9Msmo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=CG57ak7J; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="CG57ak7J" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 585A4C433C7; Sat, 27 Jan 2024 23:18:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1706397539; bh=nLv/Lkbz0ZvggWXuZdhZ6HHw2ZS5D46LumQ7ZmgJFR8=; h=Subject:To:Cc:From:Date:From; b=CG57ak7JUXLi5doroXxNCtA2IlyNu+d6hpUs5VK0V96qSpbkFN1/pGeYb0qUSmRzr 2wVaNRp2HnQ7aHL7npsnziB7rzF5fMb7DzjOEa0NVzwYnRaATgudZn50N8V8BsGa1v xEi3UMVbZoouepiSvOOKDcPHWxkYuSh5+wnOK1Rs= Subject: FAILED: patch "[PATCH] drm/amdgpu/gfx10: set UNORD_DISPATCH in compute MQDs" failed to apply to 6.7-stable tree To: alexander.deucher@amd.com,Feifei.Xu@amd.com Cc: From: Date: Sat, 27 Jan 2024 15:18:58 -0800 Message-ID: <2024012757-moonlight-wise-84c2@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit The patch below does not apply to the 6.7-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.7.y git checkout FETCH_HEAD git cherry-pick -x 03ff6d7238b77e5fb2b85dc5fe01d2db9eb893bd # git commit -s git send-email --to '' --in-reply-to '2024012757-moonlight-wise-84c2@gregkh' --subject-prefix 'PATCH 6.7.y' HEAD^.. Possible dependencies: 03ff6d7238b7 ("drm/amdgpu/gfx10: set UNORD_DISPATCH in compute MQDs") 91963397c49a ("drm/amdgpu: Enable tunneling on high-priority compute queues") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From 03ff6d7238b77e5fb2b85dc5fe01d2db9eb893bd Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 19 Jan 2024 12:23:55 -0500 Subject: [PATCH] drm/amdgpu/gfx10: set UNORD_DISPATCH in compute MQDs This needs to be set to 1 to avoid a potential deadlock in the GC 10.x and newer. On GC 9.x and older, this needs to be set to 0. This can lead to hangs in some mixed graphics and compute workloads. Updated firmware is also required for AQL. Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index d63cab294883..ecb622b7f970 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -6589,7 +6589,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, #ifdef __BIG_ENDIAN tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); #endif - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, prop->allow_tunneling); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 8b7fed913526..22cbfa1bdadd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -170,6 +170,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);