From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7705171B4; Thu, 8 Feb 2024 09:26:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707384393; cv=none; b=PHI+CKry0i97KO5BxKKIFBGsgbCYstjBYdhpZbRrUGpB7d/GVuQ+LFTUlaO8j2Vn2au73qYbiH9hle6KMwPKruJl+2m2wTFD3D6tFnuT4EqsTj8GCQpFYZIKVjs4jk80hNPRTRbxQEiS18peTbhfiXaZr5pT0p1D4M53576jccM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707384393; c=relaxed/simple; bh=DJn/JznV4z6gHv7cVHFcfLco3THQI2iFxeIjFcAeR5U=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=qyiDFwDryc3apqIrFexVKqFn7ZCQjU6IwgPoo0+8itNGx3xqDR4nHeKZIAksCHwjjenU1zQQI3sFzsXTZpBQ3DfVa+XiqEOy07IxNCd0TtMZy9TVpLHZOM4Sf9KDW9mIshKNl0Mus/5h7CD05V53jVs1ssGQxhRJN4nrbEAWrV8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XRu8/JvU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XRu8/JvU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B83EBC433C7; Thu, 8 Feb 2024 09:26:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707384393; bh=DJn/JznV4z6gHv7cVHFcfLco3THQI2iFxeIjFcAeR5U=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=XRu8/JvUYQ3LRRE7NieWOIEMI5jR0RbvmIng0aOkFS2Rj/gVCVdMjQ8FxxVrgvAAm 7OfNfkva16HRK8+2FS+CH3gsDZMMdRV0wVZw/l/DNIQFSUSYY/I0JATtG8G9MZY2We RrskuRl2UMdcVPeOH3EWrN3AnHO9U792zatvgVapsq4bw4zUe/rUttOW6BFW7KZ6Hu sjJEYfv8bJ5a576g7soea/ckwko3A3hietiDU5Wbi8/AP0FZciUE2cWDub69NHgcew tw0z+MTh1PaccjMqYtDwAsJIoc4wi9wmQgLBud9yMnKQXy6v9Hn9Ls3+ejIpatUunK CUuuRz17hiROA== Date: Thu, 8 Feb 2024 09:26:27 +0000 From: Simon Horman To: Jon Hunter Cc: Furong Xu <0x1207@gmail.com>, "David S. Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Joao Pinto , Serge Semin , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xfr@outlook.com, rock.xu@nio.com, "linux-tegra@vger.kernel.org" Subject: Re: [PATCH net v4] net: stmmac: xgmac: fix handling of DPP safety error for DMA channels Message-ID: <20240208092627.GP1297511@kernel.org> References: <20240203051439.1127090-1-0x1207@gmail.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Feb 07, 2024 at 11:56:26AM +0000, Jon Hunter wrote: > > On 03/02/2024 05:14, Furong Xu wrote: > > Commit 56e58d6c8a56 ("net: stmmac: Implement Safety Features in > > XGMAC core") checks and reports safety errors, but leaves the > > Data Path Parity Errors for each channel in DMA unhandled at all, lead to > > a storm of interrupt. > > Fix it by checking and clearing the DMA_DPP_Interrupt_Status register. > > > > Fixes: 56e58d6c8a56 ("net: stmmac: Implement Safety Features in XGMAC core") > > Signed-off-by: Furong Xu <0x1207@gmail.com> > > Reviewed-by: Simon Horman > > Reviewed-by: Serge Semin > > --- > > Changes in v4: > > - fix a typo name of DDPP bit, thanks Serge Semin > > > > Changes in v3: > > - code style fix, thanks Paolo Abeni > > > > Changes in v2: > > - explicit enable Data Path Parity Protection > > - add new counters to stmmac_safety_stats > > - add detailed log > > --- > > drivers/net/ethernet/stmicro/stmmac/common.h | 1 + > > .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 3 + > > .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 57 ++++++++++++++++++- > > 3 files changed, 60 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h > > index 721c1f8e892f..b4f60ab078d6 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/common.h > > +++ b/drivers/net/ethernet/stmicro/stmmac/common.h > > @@ -216,6 +216,7 @@ struct stmmac_safety_stats { > > unsigned long mac_errors[32]; > > unsigned long mtl_errors[32]; > > unsigned long dma_errors[32]; > > + unsigned long dma_dpp_errors[32]; > > }; > > /* Number of fields in Safety Stats */ > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h > > index 207ff1799f2c..5c67a3f89f08 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h > > @@ -303,6 +303,8 @@ > > #define XGMAC_RXCEIE BIT(4) > > #define XGMAC_TXCEIE BIT(0) > > #define XGMAC_MTL_ECC_INT_STATUS 0x000010cc > > +#define XGMAC_MTL_DPP_CONTROL 0x000010e0 > > +#define XGMAC_DPP_DISABLE BIT(0) > > #define XGMAC_MTL_TXQ_OPMODE(x) (0x00001100 + (0x80 * (x))) > > #define XGMAC_TQS GENMASK(25, 16) > > #define XGMAC_TQS_SHIFT 16 > > @@ -385,6 +387,7 @@ > > #define XGMAC_DCEIE BIT(1) > > #define XGMAC_TCEIE BIT(0) > > #define XGMAC_DMA_ECC_INT_STATUS 0x0000306c > > +#define XGMAC_DMA_DPP_INT_STATUS 0x00003074 > > #define XGMAC_DMA_CH_CONTROL(x) (0x00003100 + (0x80 * (x))) > > #define XGMAC_SPH BIT(24) > > #define XGMAC_PBLx8 BIT(16) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c > > index eb48211d9b0e..04d7c4dc2e35 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c > > @@ -830,6 +830,43 @@ static const struct dwxgmac3_error_desc dwxgmac3_dma_errors[32]= { > > { false, "UNKNOWN", "Unknown Error" }, /* 31 */ > > }; > > +static const char * const dpp_rx_err = "Read Rx Descriptor Parity checker Error"; > > +static const char * const dpp_tx_err = "Read Tx Descriptor Parity checker Error"; > > +static const struct dwxgmac3_error_desc dwxgmac3_dma_dpp_errors[32] = { > > + { true, "TDPES0", dpp_tx_err }, > > + { true, "TDPES1", dpp_tx_err }, > > + { true, "TDPES2", dpp_tx_err }, > > + { true, "TDPES3", dpp_tx_err }, > > + { true, "TDPES4", dpp_tx_err }, > > + { true, "TDPES5", dpp_tx_err }, > > + { true, "TDPES6", dpp_tx_err }, > > + { true, "TDPES7", dpp_tx_err }, > > + { true, "TDPES8", dpp_tx_err }, > > + { true, "TDPES9", dpp_tx_err }, > > + { true, "TDPES10", dpp_tx_err }, > > + { true, "TDPES11", dpp_tx_err }, > > + { true, "TDPES12", dpp_tx_err }, > > + { true, "TDPES13", dpp_tx_err }, > > + { true, "TDPES14", dpp_tx_err }, > > + { true, "TDPES15", dpp_tx_err }, > > + { true, "RDPES0", dpp_rx_err }, > > + { true, "RDPES1", dpp_rx_err }, > > + { true, "RDPES2", dpp_rx_err }, > > + { true, "RDPES3", dpp_rx_err }, > > + { true, "RDPES4", dpp_rx_err }, > > + { true, "RDPES5", dpp_rx_err }, > > + { true, "RDPES6", dpp_rx_err }, > > + { true, "RDPES7", dpp_rx_err }, > > + { true, "RDPES8", dpp_rx_err }, > > + { true, "RDPES9", dpp_rx_err }, > > + { true, "RDPES10", dpp_rx_err }, > > + { true, "RDPES11", dpp_rx_err }, > > + { true, "RDPES12", dpp_rx_err }, > > + { true, "RDPES13", dpp_rx_err }, > > + { true, "RDPES14", dpp_rx_err }, > > + { true, "RDPES15", dpp_rx_err }, > > +}; > > + > > static void dwxgmac3_handle_dma_err(struct net_device *ndev, > > void __iomem *ioaddr, bool correctable, > > struct stmmac_safety_stats *stats) > > @@ -841,6 +878,13 @@ static void dwxgmac3_handle_dma_err(struct net_device *ndev, > > dwxgmac3_log_error(ndev, value, correctable, "DMA", > > dwxgmac3_dma_errors, STAT_OFF(dma_errors), stats); > > + > > + value = readl(ioaddr + XGMAC_DMA_DPP_INT_STATUS); > > + writel(value, ioaddr + XGMAC_DMA_DPP_INT_STATUS); > > + > > + dwxgmac3_log_error(ndev, value, false, "DMA_DPP", > > + dwxgmac3_dma_dpp_errors, > > + STAT_OFF(dma_dpp_errors), stats); > > } > > static int > > @@ -881,6 +925,12 @@ dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp, > > value |= XGMAC_TMOUTEN; /* FSM Timeout Feature */ > > writel(value, ioaddr + XGMAC_MAC_FSM_CONTROL); > > + /* 5. Enable Data Path Parity Protection */ > > + value = readl(ioaddr + XGMAC_MTL_DPP_CONTROL); > > + /* already enabled by default, explicit enable it again */ > > + value &= ~XGMAC_DPP_DISABLE; > > + writel(value, ioaddr + XGMAC_MTL_DPP_CONTROL); > > + > > return 0; > > } > > @@ -914,7 +964,11 @@ static int dwxgmac3_safety_feat_irq_status(struct net_device *ndev, > > ret |= !corr; > > } > > - err = dma & (XGMAC_DEUIS | XGMAC_DECIS); > > + /* DMA_DPP_Interrupt_Status is indicated by MCSIS bit in > > + * DMA_Safety_Interrupt_Status, so we handle DMA Data Path > > + * Parity Errors here > > + */ > > + err = dma & (XGMAC_DEUIS | XGMAC_DECIS | XGMAC_MCSIS); > > corr = dma & XGMAC_DECIS; > > if (err) { > > dwxgmac3_handle_dma_err(ndev, ioaddr, corr, stats); > > @@ -930,6 +984,7 @@ static const struct dwxgmac3_error { > > { dwxgmac3_mac_errors }, > > { dwxgmac3_mtl_errors }, > > { dwxgmac3_dma_errors }, > > + { dwxgmac3_dma_dpp_errors }, > > }; > > static int dwxgmac3_safety_feat_dump(struct stmmac_safety_stats *stats, > > > This change is breaking the build on some of our builders that are still using GCC 6.x ... > > drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:836:20: error: initialiser element is not constant > { true, "TDPES0", dpp_tx_err }, > ^~~~~~~~~~ > drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:836:20: note: (near initialisation for ‘dwxgmac3_dma_dpp_errors[0].detailed_desc’) > drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:837:20: error: initialiser element is not constant > { true, "TDPES1", dpp_tx_err }, > ^~~~~~~~~~ > drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:837:20: note: (near initialisation for ‘dwxgmac3_dma_dpp_errors[1].detailed_desc’) > ... > > I know that this is quite old but the minimum supported by the kernel is v5.1 ... > > https://www.kernel.org/doc/html/next/process/changes.html Thanks Jon, I separately received a notification about this occurring with gcc 7. https://lore.kernel.org/oe-kbuild-all/202402081135.lAxxBXHk-lkp@intel.com/ It is unclear to me why this occurs, as dpp_tx_err and dpp_tx_err are const. But I do seem to be able to address this problem by using #defines for these values instead. I plan to post a patch shortly. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9738C4828F for ; Thu, 8 Feb 2024 09:26:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mTdqpOTbeMlLKrWjqLxxl1G22R0zyUepUmy8tsdmqps=; b=uLNIxys6hjX5OF cQ7N7aMdz7OQDmOtOhKiilQnzMVJzkCgUu7R+W9ovFJZKdQzqH/feA7TixYVmQUiGZnJBicUZbpBq UoJWzQMZSZ6ilYmAB5iODZj6ipdYdvfLsshZxZk/Pp16KhafiZKMZdAtK6507FOq0GifWzpOoTAq/ BivFdCq6BhVg+CXCDNgwiaoWi98d5OMM+Vc1qpxQxyMABpRddKFHydlbS2RCTUoB0ARq3/fBQ01jm 7688YRlZxe/jOs+xYCIzoDGWRRNrU9rA6JcIfFsybCSCsoG+OAkZf1CKJ7bjmPKpHVD09fzNr3JY6 JJnoteAStjGrqiZfsNtQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rY0g2-0000000DBwb-2ZSP; Thu, 08 Feb 2024 09:26:38 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rY0g0-0000000DBvR-09Ab for linux-arm-kernel@lists.infradead.org; Thu, 08 Feb 2024 09:26:37 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id E5E66CE1BB0; Thu, 8 Feb 2024 09:26:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B83EBC433C7; Thu, 8 Feb 2024 09:26:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707384393; bh=DJn/JznV4z6gHv7cVHFcfLco3THQI2iFxeIjFcAeR5U=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=XRu8/JvUYQ3LRRE7NieWOIEMI5jR0RbvmIng0aOkFS2Rj/gVCVdMjQ8FxxVrgvAAm 7OfNfkva16HRK8+2FS+CH3gsDZMMdRV0wVZw/l/DNIQFSUSYY/I0JATtG8G9MZY2We RrskuRl2UMdcVPeOH3EWrN3AnHO9U792zatvgVapsq4bw4zUe/rUttOW6BFW7KZ6Hu sjJEYfv8bJ5a576g7soea/ckwko3A3hietiDU5Wbi8/AP0FZciUE2cWDub69NHgcew tw0z+MTh1PaccjMqYtDwAsJIoc4wi9wmQgLBud9yMnKQXy6v9Hn9Ls3+ejIpatUunK CUuuRz17hiROA== Date: Thu, 8 Feb 2024 09:26:27 +0000 From: Simon Horman To: Jon Hunter Cc: Furong Xu <0x1207@gmail.com>, "David S. Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Joao Pinto , Serge Semin , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xfr@outlook.com, rock.xu@nio.com, "linux-tegra@vger.kernel.org" Subject: Re: [PATCH net v4] net: stmmac: xgmac: fix handling of DPP safety error for DMA channels Message-ID: <20240208092627.GP1297511@kernel.org> References: <20240203051439.1127090-1-0x1207@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240208_012636_464196_D04A7A0B X-CRM114-Status: GOOD ( 34.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gV2VkLCBGZWIgMDcsIDIwMjQgYXQgMTE6NTY6MjZBTSArMDAwMCwgSm9uIEh1bnRlciB3cm90 ZToKPiAKPiBPbiAwMy8wMi8yMDI0IDA1OjE0LCBGdXJvbmcgWHUgd3JvdGU6Cj4gPiBDb21taXQg NTZlNThkNmM4YTU2ICgibmV0OiBzdG1tYWM6IEltcGxlbWVudCBTYWZldHkgRmVhdHVyZXMgaW4K PiA+IFhHTUFDIGNvcmUiKSBjaGVja3MgYW5kIHJlcG9ydHMgc2FmZXR5IGVycm9ycywgYnV0IGxl YXZlcyB0aGUKPiA+IERhdGEgUGF0aCBQYXJpdHkgRXJyb3JzIGZvciBlYWNoIGNoYW5uZWwgaW4g RE1BIHVuaGFuZGxlZCBhdCBhbGwsIGxlYWQgdG8KPiA+IGEgc3Rvcm0gb2YgaW50ZXJydXB0Lgo+ ID4gRml4IGl0IGJ5IGNoZWNraW5nIGFuZCBjbGVhcmluZyB0aGUgRE1BX0RQUF9JbnRlcnJ1cHRf U3RhdHVzIHJlZ2lzdGVyLgo+ID4gCj4gPiBGaXhlczogNTZlNThkNmM4YTU2ICgibmV0OiBzdG1t YWM6IEltcGxlbWVudCBTYWZldHkgRmVhdHVyZXMgaW4gWEdNQUMgY29yZSIpCj4gPiBTaWduZWQt b2ZmLWJ5OiBGdXJvbmcgWHUgPDB4MTIwN0BnbWFpbC5jb20+Cj4gPiBSZXZpZXdlZC1ieTogU2lt b24gSG9ybWFuIDxob3Jtc0BrZXJuZWwub3JnPgo+ID4gUmV2aWV3ZWQtYnk6IFNlcmdlIFNlbWlu IDxmYW5jZXIubGFuY2VyQGdtYWlsLmNvbT4KPiA+IC0tLQo+ID4gQ2hhbmdlcyBpbiB2NDoKPiA+ ICAgLSBmaXggYSB0eXBvIG5hbWUgb2YgRERQUCBiaXQsIHRoYW5rcyBTZXJnZSBTZW1pbgo+ID4g Cj4gPiBDaGFuZ2VzIGluIHYzOgo+ID4gICAtIGNvZGUgc3R5bGUgZml4LCB0aGFua3MgUGFvbG8g QWJlbmkKPiA+IAo+ID4gQ2hhbmdlcyBpbiB2MjoKPiA+ICAgIC0gZXhwbGljaXQgZW5hYmxlIERh dGEgUGF0aCBQYXJpdHkgUHJvdGVjdGlvbgo+ID4gICAgLSBhZGQgbmV3IGNvdW50ZXJzIHRvIHN0 bW1hY19zYWZldHlfc3RhdHMKPiA+ICAgIC0gYWRkIGRldGFpbGVkIGxvZwo+ID4gLS0tCj4gPiAg IGRyaXZlcnMvbmV0L2V0aGVybmV0L3N0bWljcm8vc3RtbWFjL2NvbW1vbi5oICB8ICAxICsKPiA+ ICAgLi4uL25ldC9ldGhlcm5ldC9zdG1pY3JvL3N0bW1hYy9kd3hnbWFjMi5oICAgIHwgIDMgKwo+ ID4gICAuLi4vZXRoZXJuZXQvc3RtaWNyby9zdG1tYWMvZHd4Z21hYzJfY29yZS5jICAgfCA1NyAr KysrKysrKysrKysrKysrKystCj4gPiAgIDMgZmlsZXMgY2hhbmdlZCwgNjAgaW5zZXJ0aW9ucygr KSwgMSBkZWxldGlvbigtKQo+ID4gCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9uZXQvZXRoZXJu ZXQvc3RtaWNyby9zdG1tYWMvY29tbW9uLmggYi9kcml2ZXJzL25ldC9ldGhlcm5ldC9zdG1pY3Jv L3N0bW1hYy9jb21tb24uaAo+ID4gaW5kZXggNzIxYzFmOGU4OTJmLi5iNGY2MGFiMDc4ZDYgMTAw NjQ0Cj4gPiAtLS0gYS9kcml2ZXJzL25ldC9ldGhlcm5ldC9zdG1pY3JvL3N0bW1hYy9jb21tb24u aAo+ID4gKysrIGIvZHJpdmVycy9uZXQvZXRoZXJuZXQvc3RtaWNyby9zdG1tYWMvY29tbW9uLmgK PiA+IEBAIC0yMTYsNiArMjE2LDcgQEAgc3RydWN0IHN0bW1hY19zYWZldHlfc3RhdHMgewo+ID4g ICAJdW5zaWduZWQgbG9uZyBtYWNfZXJyb3JzWzMyXTsKPiA+ICAgCXVuc2lnbmVkIGxvbmcgbXRs X2Vycm9yc1szMl07Cj4gPiAgIAl1bnNpZ25lZCBsb25nIGRtYV9lcnJvcnNbMzJdOwo+ID4gKwl1 bnNpZ25lZCBsb25nIGRtYV9kcHBfZXJyb3JzWzMyXTsKPiA+ICAgfTsKPiA+ICAgLyogTnVtYmVy IG9mIGZpZWxkcyBpbiBTYWZldHkgU3RhdHMgKi8KPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL25l dC9ldGhlcm5ldC9zdG1pY3JvL3N0bW1hYy9kd3hnbWFjMi5oIGIvZHJpdmVycy9uZXQvZXRoZXJu ZXQvc3RtaWNyby9zdG1tYWMvZHd4Z21hYzIuaAo+ID4gaW5kZXggMjA3ZmYxNzk5ZjJjLi41YzY3 YTNmODlmMDggMTAwNjQ0Cj4gPiAtLS0gYS9kcml2ZXJzL25ldC9ldGhlcm5ldC9zdG1pY3JvL3N0 bW1hYy9kd3hnbWFjMi5oCj4gPiArKysgYi9kcml2ZXJzL25ldC9ldGhlcm5ldC9zdG1pY3JvL3N0 bW1hYy9kd3hnbWFjMi5oCj4gPiBAQCAtMzAzLDYgKzMwMyw4IEBACj4gPiAgICNkZWZpbmUgWEdN QUNfUlhDRUlFCQkJQklUKDQpCj4gPiAgICNkZWZpbmUgWEdNQUNfVFhDRUlFCQkJQklUKDApCj4g PiAgICNkZWZpbmUgWEdNQUNfTVRMX0VDQ19JTlRfU1RBVFVTCTB4MDAwMDEwY2MKPiA+ICsjZGVm aW5lIFhHTUFDX01UTF9EUFBfQ09OVFJPTAkJMHgwMDAwMTBlMAo+ID4gKyNkZWZpbmUgWEdNQUNf RFBQX0RJU0FCTEUJCUJJVCgwKQo+ID4gICAjZGVmaW5lIFhHTUFDX01UTF9UWFFfT1BNT0RFKHgp CQkoMHgwMDAwMTEwMCArICgweDgwICogKHgpKSkKPiA+ICAgI2RlZmluZSBYR01BQ19UUVMJCQlH RU5NQVNLKDI1LCAxNikKPiA+ICAgI2RlZmluZSBYR01BQ19UUVNfU0hJRlQJCQkxNgo+ID4gQEAg LTM4NSw2ICszODcsNyBAQAo+ID4gICAjZGVmaW5lIFhHTUFDX0RDRUlFCQkJQklUKDEpCj4gPiAg ICNkZWZpbmUgWEdNQUNfVENFSUUJCQlCSVQoMCkKPiA+ICAgI2RlZmluZSBYR01BQ19ETUFfRUND X0lOVF9TVEFUVVMJMHgwMDAwMzA2Ywo+ID4gKyNkZWZpbmUgWEdNQUNfRE1BX0RQUF9JTlRfU1RB VFVTCTB4MDAwMDMwNzQKPiA+ICAgI2RlZmluZSBYR01BQ19ETUFfQ0hfQ09OVFJPTCh4KQkJKDB4 MDAwMDMxMDAgKyAoMHg4MCAqICh4KSkpCj4gPiAgICNkZWZpbmUgWEdNQUNfU1BICQkJQklUKDI0 KQo+ID4gICAjZGVmaW5lIFhHTUFDX1BCTHg4CQkJQklUKDE2KQo+ID4gZGlmZiAtLWdpdCBhL2Ry aXZlcnMvbmV0L2V0aGVybmV0L3N0bWljcm8vc3RtbWFjL2R3eGdtYWMyX2NvcmUuYyBiL2RyaXZl cnMvbmV0L2V0aGVybmV0L3N0bWljcm8vc3RtbWFjL2R3eGdtYWMyX2NvcmUuYwo+ID4gaW5kZXgg ZWI0ODIxMWQ5YjBlLi4wNGQ3YzRkYzJlMzUgMTAwNjQ0Cj4gPiAtLS0gYS9kcml2ZXJzL25ldC9l dGhlcm5ldC9zdG1pY3JvL3N0bW1hYy9kd3hnbWFjMl9jb3JlLmMKPiA+ICsrKyBiL2RyaXZlcnMv bmV0L2V0aGVybmV0L3N0bWljcm8vc3RtbWFjL2R3eGdtYWMyX2NvcmUuYwo+ID4gQEAgLTgzMCw2 ICs4MzAsNDMgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBkd3hnbWFjM19lcnJvcl9kZXNjIGR3eGdt YWMzX2RtYV9lcnJvcnNbMzJdPSB7Cj4gPiAgIAl7IGZhbHNlLCAiVU5LTk9XTiIsICJVbmtub3du IEVycm9yIiB9LCAvKiAzMSAqLwo+ID4gICB9Owo+ID4gK3N0YXRpYyBjb25zdCBjaGFyICogY29u c3QgZHBwX3J4X2VyciA9ICJSZWFkIFJ4IERlc2NyaXB0b3IgUGFyaXR5IGNoZWNrZXIgRXJyb3Ii Owo+ID4gK3N0YXRpYyBjb25zdCBjaGFyICogY29uc3QgZHBwX3R4X2VyciA9ICJSZWFkIFR4IERl c2NyaXB0b3IgUGFyaXR5IGNoZWNrZXIgRXJyb3IiOwo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg ZHd4Z21hYzNfZXJyb3JfZGVzYyBkd3hnbWFjM19kbWFfZHBwX2Vycm9yc1szMl0gPSB7Cj4gPiAr CXsgdHJ1ZSwgIlREUEVTMCIsIGRwcF90eF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiVERQRVMxIiwg ZHBwX3R4X2VyciB9LAo+ID4gKwl7IHRydWUsICJURFBFUzIiLCBkcHBfdHhfZXJyIH0sCj4gPiAr CXsgdHJ1ZSwgIlREUEVTMyIsIGRwcF90eF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiVERQRVM0Iiwg ZHBwX3R4X2VyciB9LAo+ID4gKwl7IHRydWUsICJURFBFUzUiLCBkcHBfdHhfZXJyIH0sCj4gPiAr CXsgdHJ1ZSwgIlREUEVTNiIsIGRwcF90eF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiVERQRVM3Iiwg ZHBwX3R4X2VyciB9LAo+ID4gKwl7IHRydWUsICJURFBFUzgiLCBkcHBfdHhfZXJyIH0sCj4gPiAr CXsgdHJ1ZSwgIlREUEVTOSIsIGRwcF90eF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiVERQRVMxMCIs IGRwcF90eF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiVERQRVMxMSIsIGRwcF90eF9lcnIgfSwKPiA+ ICsJeyB0cnVlLCAiVERQRVMxMiIsIGRwcF90eF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiVERQRVMx MyIsIGRwcF90eF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiVERQRVMxNCIsIGRwcF90eF9lcnIgfSwK PiA+ICsJeyB0cnVlLCAiVERQRVMxNSIsIGRwcF90eF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiUkRQ RVMwIiwgZHBwX3J4X2VyciB9LAo+ID4gKwl7IHRydWUsICJSRFBFUzEiLCBkcHBfcnhfZXJyIH0s Cj4gPiArCXsgdHJ1ZSwgIlJEUEVTMiIsIGRwcF9yeF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiUkRQ RVMzIiwgZHBwX3J4X2VyciB9LAo+ID4gKwl7IHRydWUsICJSRFBFUzQiLCBkcHBfcnhfZXJyIH0s Cj4gPiArCXsgdHJ1ZSwgIlJEUEVTNSIsIGRwcF9yeF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiUkRQ RVM2IiwgZHBwX3J4X2VyciB9LAo+ID4gKwl7IHRydWUsICJSRFBFUzciLCBkcHBfcnhfZXJyIH0s Cj4gPiArCXsgdHJ1ZSwgIlJEUEVTOCIsIGRwcF9yeF9lcnIgfSwKPiA+ICsJeyB0cnVlLCAiUkRQ RVM5IiwgZHBwX3J4X2VyciB9LAo+ID4gKwl7IHRydWUsICJSRFBFUzEwIiwgZHBwX3J4X2VyciB9 LAo+ID4gKwl7IHRydWUsICJSRFBFUzExIiwgZHBwX3J4X2VyciB9LAo+ID4gKwl7IHRydWUsICJS RFBFUzEyIiwgZHBwX3J4X2VyciB9LAo+ID4gKwl7IHRydWUsICJSRFBFUzEzIiwgZHBwX3J4X2Vy ciB9LAo+ID4gKwl7IHRydWUsICJSRFBFUzE0IiwgZHBwX3J4X2VyciB9LAo+ID4gKwl7IHRydWUs ICJSRFBFUzE1IiwgZHBwX3J4X2VyciB9LAo+ID4gK307Cj4gPiArCj4gPiAgIHN0YXRpYyB2b2lk IGR3eGdtYWMzX2hhbmRsZV9kbWFfZXJyKHN0cnVjdCBuZXRfZGV2aWNlICpuZGV2LAo+ID4gICAJ CQkJICAgIHZvaWQgX19pb21lbSAqaW9hZGRyLCBib29sIGNvcnJlY3RhYmxlLAo+ID4gICAJCQkJ ICAgIHN0cnVjdCBzdG1tYWNfc2FmZXR5X3N0YXRzICpzdGF0cykKPiA+IEBAIC04NDEsNiArODc4 LDEzIEBAIHN0YXRpYyB2b2lkIGR3eGdtYWMzX2hhbmRsZV9kbWFfZXJyKHN0cnVjdCBuZXRfZGV2 aWNlICpuZGV2LAo+ID4gICAJZHd4Z21hYzNfbG9nX2Vycm9yKG5kZXYsIHZhbHVlLCBjb3JyZWN0 YWJsZSwgIkRNQSIsCj4gPiAgIAkJCSAgIGR3eGdtYWMzX2RtYV9lcnJvcnMsIFNUQVRfT0ZGKGRt YV9lcnJvcnMpLCBzdGF0cyk7Cj4gPiArCj4gPiArCXZhbHVlID0gcmVhZGwoaW9hZGRyICsgWEdN QUNfRE1BX0RQUF9JTlRfU1RBVFVTKTsKPiA+ICsJd3JpdGVsKHZhbHVlLCBpb2FkZHIgKyBYR01B Q19ETUFfRFBQX0lOVF9TVEFUVVMpOwo+ID4gKwo+ID4gKwlkd3hnbWFjM19sb2dfZXJyb3IobmRl diwgdmFsdWUsIGZhbHNlLCAiRE1BX0RQUCIsCj4gPiArCQkJICAgZHd4Z21hYzNfZG1hX2RwcF9l cnJvcnMsCj4gPiArCQkJICAgU1RBVF9PRkYoZG1hX2RwcF9lcnJvcnMpLCBzdGF0cyk7Cj4gPiAg IH0KPiA+ICAgc3RhdGljIGludAo+ID4gQEAgLTg4MSw2ICs5MjUsMTIgQEAgZHd4Z21hYzNfc2Fm ZXR5X2ZlYXRfY29uZmlnKHZvaWQgX19pb21lbSAqaW9hZGRyLCB1bnNpZ25lZCBpbnQgYXNwLAo+ ID4gICAJdmFsdWUgfD0gWEdNQUNfVE1PVVRFTjsgLyogRlNNIFRpbWVvdXQgRmVhdHVyZSAqLwo+ ID4gICAJd3JpdGVsKHZhbHVlLCBpb2FkZHIgKyBYR01BQ19NQUNfRlNNX0NPTlRST0wpOwo+ID4g KwkvKiA1LiBFbmFibGUgRGF0YSBQYXRoIFBhcml0eSBQcm90ZWN0aW9uICovCj4gPiArCXZhbHVl ID0gcmVhZGwoaW9hZGRyICsgWEdNQUNfTVRMX0RQUF9DT05UUk9MKTsKPiA+ICsJLyogYWxyZWFk eSBlbmFibGVkIGJ5IGRlZmF1bHQsIGV4cGxpY2l0IGVuYWJsZSBpdCBhZ2FpbiAqLwo+ID4gKwl2 YWx1ZSAmPSB+WEdNQUNfRFBQX0RJU0FCTEU7Cj4gPiArCXdyaXRlbCh2YWx1ZSwgaW9hZGRyICsg WEdNQUNfTVRMX0RQUF9DT05UUk9MKTsKPiA+ICsKPiA+ICAgCXJldHVybiAwOwo+ID4gICB9Cj4g PiBAQCAtOTE0LDcgKzk2NCwxMSBAQCBzdGF0aWMgaW50IGR3eGdtYWMzX3NhZmV0eV9mZWF0X2ly cV9zdGF0dXMoc3RydWN0IG5ldF9kZXZpY2UgKm5kZXYsCj4gPiAgIAkJcmV0IHw9ICFjb3JyOwo+ ID4gICAJfQo+ID4gLQllcnIgPSBkbWEgJiAoWEdNQUNfREVVSVMgfCBYR01BQ19ERUNJUyk7Cj4g PiArCS8qIERNQV9EUFBfSW50ZXJydXB0X1N0YXR1cyBpcyBpbmRpY2F0ZWQgYnkgTUNTSVMgYml0 IGluCj4gPiArCSAqIERNQV9TYWZldHlfSW50ZXJydXB0X1N0YXR1cywgc28gd2UgaGFuZGxlIERN QSBEYXRhIFBhdGgKPiA+ICsJICogUGFyaXR5IEVycm9ycyBoZXJlCj4gPiArCSAqLwo+ID4gKwll cnIgPSBkbWEgJiAoWEdNQUNfREVVSVMgfCBYR01BQ19ERUNJUyB8IFhHTUFDX01DU0lTKTsKPiA+ ICAgCWNvcnIgPSBkbWEgJiBYR01BQ19ERUNJUzsKPiA+ICAgCWlmIChlcnIpIHsKPiA+ICAgCQlk d3hnbWFjM19oYW5kbGVfZG1hX2VycihuZGV2LCBpb2FkZHIsIGNvcnIsIHN0YXRzKTsKPiA+IEBA IC05MzAsNiArOTg0LDcgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBkd3hnbWFjM19lcnJvciB7Cj4g PiAgIAl7IGR3eGdtYWMzX21hY19lcnJvcnMgfSwKPiA+ICAgCXsgZHd4Z21hYzNfbXRsX2Vycm9y cyB9LAo+ID4gICAJeyBkd3hnbWFjM19kbWFfZXJyb3JzIH0sCj4gPiArCXsgZHd4Z21hYzNfZG1h X2RwcF9lcnJvcnMgfSwKPiA+ICAgfTsKPiA+ICAgc3RhdGljIGludCBkd3hnbWFjM19zYWZldHlf ZmVhdF9kdW1wKHN0cnVjdCBzdG1tYWNfc2FmZXR5X3N0YXRzICpzdGF0cywKPiAKPiAKPiBUaGlz IGNoYW5nZSBpcyBicmVha2luZyB0aGUgYnVpbGQgb24gc29tZSBvZiBvdXIgYnVpbGRlcnMgdGhh dCBhcmUgc3RpbGwgdXNpbmcgR0NDIDYueCAuLi4KPiAKPiBkcml2ZXJzL25ldC9ldGhlcm5ldC9z dG1pY3JvL3N0bW1hYy9kd3hnbWFjMl9jb3JlLmM6ODM2OjIwOiBlcnJvcjogaW5pdGlhbGlzZXIg ZWxlbWVudCBpcyBub3QgY29uc3RhbnQKPiAgIHsgdHJ1ZSwgIlREUEVTMCIsIGRwcF90eF9lcnIg fSwKPiAgICAgICAgICAgICAgICAgICAgIF5+fn5+fn5+fn4KPiBkcml2ZXJzL25ldC9ldGhlcm5l dC9zdG1pY3JvL3N0bW1hYy9kd3hnbWFjMl9jb3JlLmM6ODM2OjIwOiBub3RlOiAobmVhciBpbml0 aWFsaXNhdGlvbiBmb3Ig4oCYZHd4Z21hYzNfZG1hX2RwcF9lcnJvcnNbMF0uZGV0YWlsZWRfZGVz Y+KAmSkKPiBkcml2ZXJzL25ldC9ldGhlcm5ldC9zdG1pY3JvL3N0bW1hYy9kd3hnbWFjMl9jb3Jl LmM6ODM3OjIwOiBlcnJvcjogaW5pdGlhbGlzZXIgZWxlbWVudCBpcyBub3QgY29uc3RhbnQKPiAg IHsgdHJ1ZSwgIlREUEVTMSIsIGRwcF90eF9lcnIgfSwKPiAgICAgICAgICAgICAgICAgICAgIF5+ fn5+fn5+fn4KPiBkcml2ZXJzL25ldC9ldGhlcm5ldC9zdG1pY3JvL3N0bW1hYy9kd3hnbWFjMl9j b3JlLmM6ODM3OjIwOiBub3RlOiAobmVhciBpbml0aWFsaXNhdGlvbiBmb3Ig4oCYZHd4Z21hYzNf ZG1hX2RwcF9lcnJvcnNbMV0uZGV0YWlsZWRfZGVzY+KAmSkKPiAuLi4KPiAKPiBJIGtub3cgdGhh dCB0aGlzIGlzIHF1aXRlIG9sZCBidXQgdGhlIG1pbmltdW0gc3VwcG9ydGVkIGJ5IHRoZSBrZXJu ZWwgaXMgdjUuMSAuLi4KPiAKPiBodHRwczovL3d3dy5rZXJuZWwub3JnL2RvYy9odG1sL25leHQv cHJvY2Vzcy9jaGFuZ2VzLmh0bWwKClRoYW5rcyBKb24sCgpJIHNlcGFyYXRlbHkgcmVjZWl2ZWQg YSBub3RpZmljYXRpb24gYWJvdXQgdGhpcyBvY2N1cnJpbmcgd2l0aCBnY2MgNy4KCmh0dHBzOi8v bG9yZS5rZXJuZWwub3JnL29lLWtidWlsZC1hbGwvMjAyNDAyMDgxMTM1LmxBeHhCWEhrLWxrcEBp bnRlbC5jb20vCgpJdCBpcyB1bmNsZWFyIHRvIG1lIHdoeSB0aGlzIG9jY3VycywgYXMgZHBwX3R4 X2VyciBhbmQgZHBwX3R4X2VyciBhcmUgY29uc3QuCkJ1dCBJIGRvIHNlZW0gdG8gYmUgYWJsZSB0 byBhZGRyZXNzIHRoaXMgcHJvYmxlbSBieSB1c2luZyAjZGVmaW5lcyBmb3IKdGhlc2UgdmFsdWVz IGluc3RlYWQuCgpJIHBsYW4gdG8gcG9zdCBhIHBhdGNoIHNob3J0bHkuCgpfX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxp bmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3Rz LmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==