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client-ip=192.168.10.10; helo=twmbx02.aspeed.com; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX02.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: mici8kZSpTB7 v1: 1. support uart controller both 0 and 1 base 2. fix hardcode boot address 0 v2: 1. introduce a new UART0 device name 2. remove ASPEED_SOC_SPI_BOOT_ADDR marco v3: 1. add uart helper functions to get the index, start and last. 2. add more description in commit log Jamin Lin (2): aspeed: introduce a new UART0 device name aspeed: fix hardcode boot address 0 hw/arm/aspeed.c | 17 +++++++++++------ hw/arm/aspeed_ast10x0.c | 1 + hw/arm/aspeed_ast2400.c | 6 ++++-- hw/arm/aspeed_ast2600.c | 3 ++- hw/arm/aspeed_soc_common.c | 10 ++++++---- include/hw/arm/aspeed_soc.h | 19 +++++++++++++++++-- 6 files changed, 41 insertions(+), 15 deletions(-) -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4DFCC4829E for ; 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client-ip=192.168.10.10; helo=twmbx02.aspeed.com; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX02.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org v1: 1. support uart controller both 0 and 1 base 2. fix hardcode boot address 0 v2: 1. introduce a new UART0 device name 2. remove ASPEED_SOC_SPI_BOOT_ADDR marco v3: 1. add uart helper functions to get the index, start and last. 2. add more description in commit log Jamin Lin (2): aspeed: introduce a new UART0 device name aspeed: fix hardcode boot address 0 hw/arm/aspeed.c | 17 +++++++++++------ hw/arm/aspeed_ast10x0.c | 1 + hw/arm/aspeed_ast2400.c | 6 ++++-- hw/arm/aspeed_ast2600.c | 3 ++- hw/arm/aspeed_soc_common.c | 10 ++++++---- include/hw/arm/aspeed_soc.h | 19 +++++++++++++++++-- 6 files changed, 41 insertions(+), 15 deletions(-) -- 2.25.1