From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Cc: <linux-efi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-cxl@vger.kernel.org>, Ard Biesheuvel <ardb@kernel.org>,
"Alison Schofield" <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Yazen Ghannam <yazen.ghannam@amd.com>
Subject: Re: [PATCH v2 2/4] efi/cper, cxl: Make definitions and structures global
Date: Thu, 15 Feb 2024 11:58:38 +0000 [thread overview]
Message-ID: <20240215115838.000050b1@Huawei.com> (raw)
In-Reply-To: <20240109034755.100555-3-Smita.KoralahalliChannabasappa@amd.com>
On Tue, 9 Jan 2024 03:47:53 +0000
Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> wrote:
> In preparation to add tracepoint support, move protocol error UUID
> definition to a common location and make CXL RAS capability struct
> global for use across different modules.
>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> v2:
> No change.
> ---
> drivers/firmware/efi/cper_cxl.c | 11 -----------
> drivers/firmware/efi/cper_cxl.h | 7 ++-----
> include/linux/cper.h | 4 ++++
> include/linux/cxl-event.h | 11 +++++++++++
> 4 files changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cxl.c
> index a55771b99a97..4fd8d783993e 100644
> --- a/drivers/firmware/efi/cper_cxl.c
> +++ b/drivers/firmware/efi/cper_cxl.c
> @@ -18,17 +18,6 @@
> #define PROT_ERR_VALID_DVSEC BIT_ULL(5)
> #define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6)
>
> -/* CXL RAS Capability Structure, CXL v3.0 sec 8.2.4.16 */
> -struct cxl_ras_capability_regs {
> - u32 uncor_status;
> - u32 uncor_mask;
> - u32 uncor_severity;
> - u32 cor_status;
> - u32 cor_mask;
> - u32 cap_control;
> - u32 header_log[16];
> -};
> -
> static const char * const prot_err_agent_type_strs[] = {
> "Restricted CXL Device",
> "Restricted CXL Host Downstream Port",
> diff --git a/drivers/firmware/efi/cper_cxl.h b/drivers/firmware/efi/cper_cxl.h
> index 86bfcf7909ec..6f8c00495708 100644
> --- a/drivers/firmware/efi/cper_cxl.h
> +++ b/drivers/firmware/efi/cper_cxl.h
> @@ -7,14 +7,11 @@
> * Author: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
> */
>
> +#include <linux/cxl-event.h>
> +
> #ifndef LINUX_CPER_CXL_H
> #define LINUX_CPER_CXL_H
>
> -/* CXL Protocol Error Section */
> -#define CPER_SEC_CXL_PROT_ERR \
> - GUID_INIT(0x80B9EFB4, 0x52B5, 0x4DE3, 0xA7, 0x77, 0x68, 0x78, \
> - 0x4B, 0x77, 0x10, 0x48)
> -
> #pragma pack(1)
>
> /* Compute Express Link Protocol Error Section, UEFI v2.10 sec N.2.13 */
> diff --git a/include/linux/cper.h b/include/linux/cper.h
> index c1a7dc325121..2cbf0a93785a 100644
> --- a/include/linux/cper.h
> +++ b/include/linux/cper.h
> @@ -89,6 +89,10 @@ enum {
> #define CPER_NOTIFY_DMAR \
> GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \
> 0x72, 0x2D, 0xEB, 0x41)
> +/* CXL Protocol Error Section */
> +#define CPER_SEC_CXL_PROT_ERR \
> + GUID_INIT(0x80B9EFB4, 0x52B5, 0x4DE3, 0xA7, 0x77, 0x68, 0x78, \
> + 0x4B, 0x77, 0x10, 0x48)
>
> /*
> * Flags bits definitions for flags in struct cper_record_header
> diff --git a/include/linux/cxl-event.h b/include/linux/cxl-event.h
> index 6ce839c59749..3a41dd5723e8 100644
> --- a/include/linux/cxl-event.h
> +++ b/include/linux/cxl-event.h
> @@ -141,6 +141,17 @@ struct cxl_cper_event_rec {
> union cxl_event event;
> } __packed;
>
> +/* CXL RAS Capability Structure, CXL v3.0 sec 8.2.4.16 */
> +struct cxl_ras_capability_regs {
> + u32 uncor_status;
> + u32 uncor_mask;
> + u32 uncor_severity;
> + u32 cor_status;
> + u32 cor_mask;
> + u32 cap_control;
> + u32 header_log[16];
> +};
> +
> struct cxl_cper_event_info {
> struct cxl_cper_event_rec rec;
> };
next prev parent reply other threads:[~2024-02-15 11:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-09 3:47 [PATCH v2 0/4] acpi/ghes, cper, cxl: Trace FW-First CXL Protocol Errors Smita Koralahalli
2024-01-09 3:47 ` [PATCH v2 1/4] acpi/ghes, cxl: Create a common CXL struct to handle different CXL CPER records Smita Koralahalli
2024-02-15 11:56 ` Jonathan Cameron
2024-01-09 3:47 ` [PATCH v2 2/4] efi/cper, cxl: Make definitions and structures global Smita Koralahalli
2024-02-15 11:58 ` Jonathan Cameron [this message]
2024-02-15 14:47 ` Ard Biesheuvel
2024-01-09 3:47 ` [PATCH v2 3/4] acpi/ghes, efi/cper: Recognize and process CXL Protocol Errors Smita Koralahalli
2024-02-15 12:17 ` Jonathan Cameron
2024-01-09 3:47 ` [PATCH v2 4/4] acpi/ghes, cxl/pci: Trace FW-First " Smita Koralahalli
2024-02-15 12:22 ` Jonathan Cameron
2024-05-07 9:35 ` [PATCH v2 0/4] acpi/ghes, cper, cxl: " Fabio M. De Francesco
2024-05-16 17:59 ` Smita Koralahalli
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