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From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Uma Shankar" <uma.shankar@intel.com>
Subject: [PATCH v2 01/21] drm/dp: Add drm_dp_max_dprx_data_rate()
Date: Tue, 20 Feb 2024 23:18:21 +0200	[thread overview]
Message-ID: <20240220211841.448846-2-imre.deak@intel.com> (raw)
In-Reply-To: <20240220211841.448846-1-imre.deak@intel.com>

Copy intel_dp_max_data_rate() to DRM core. It will be needed by a
follow-up DP tunnel patch, checking the maximum rate the DPRX (sink)
supports. Accordingly use the drm_dp_max_dprx_data_rate() name for
clarity. This patchset will also switch calling the new DRM function
in i915 instead of intel_dp_max_data_rate().

While at it simplify the function documentation/comments, removing
parts described already by drm_dp_bw_channel_coding_efficiency().

v2: (Ville)
- Remove max_link_rate_kbps.
- Simplify the function documentation.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 30 +++++++++++++++++++++++++
 include/drm/display/drm_dp_helper.h     |  2 ++
 2 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 8d6ce46471ae6..d046dfa79504f 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -4055,3 +4055,33 @@ int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
 		return 800000;
 }
 EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
+
+/**
+ * drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink
+ * @max_link_rate: max DPRX link rate in 10kbps units
+ * @max_lanes: max DPRX lane count
+ *
+ * Given a link rate and lanes, get the data bandwidth.
+ *
+ * Data bandwidth is the actual payload rate, which depends on the data
+ * bandwidth efficiency and the link rate.
+ *
+ * Note that protocol layers above the DPRX link level considered here can
+ * further limit the maximum data rate. Such layers are the MST topology (with
+ * limits on the link between the source and first branch device as well as on
+ * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -
+ * which in turn can encapsulate an MST link with its own limit - with each
+ * SST or MST encapsulated tunnel sharing the BW of a tunnel group.
+ *
+ * Returns the maximum data rate in kBps units.
+ */
+int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes)
+{
+	int ch_coding_efficiency =
+		drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
+
+	return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
+					      ch_coding_efficiency),
+				  1000000 * 8);
+}
+EXPORT_SYMBOL(drm_dp_max_dprx_data_rate);
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index d02014a87f127..65dae9a9f2fb6 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -812,4 +812,6 @@ int drm_dp_bw_overhead(int lane_count, int hactive,
 		       int bpp_x16, unsigned long flags);
 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
 
+int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
+
 #endif /* _DRM_DP_HELPER_H_ */
-- 
2.39.2


  reply	other threads:[~2024-02-20 21:18 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-20 21:18 [PATCH v2 00/21] drm/i915: Add Display Port tunnel BW allocation support Imre Deak
2024-02-20 21:18 ` Imre Deak [this message]
2024-02-26 18:52   ` [PATCH v3 01/21] drm/dp: Add drm_dp_max_dprx_data_rate() Imre Deak
2024-02-20 21:18 ` [PATCH v2 02/21] drm/dp: Add support for DP tunneling Imre Deak
2024-02-23  6:25   ` Shankar, Uma
2024-02-23 14:33     ` Imre Deak
2024-02-23 21:32   ` Ville Syrjälä
2024-02-26 11:40     ` Imre Deak
2024-02-26 18:52   ` [PATCH v3 " Imre Deak
2024-02-20 21:18 ` [PATCH v2 03/21] drm/i915: Fix display bpp limit computation during system resume Imre Deak
2024-02-23  6:38   ` Shankar, Uma
2024-02-20 21:18 ` [PATCH v2 04/21] drm/i915/dp: Add support to notify MST connectors to retry modesets Imre Deak
2024-02-23  7:59   ` Shankar, Uma
2024-02-20 21:18 ` [PATCH v2 05/21] drm/i915/dp: Use drm_dp_max_dprx_data_rate() Imre Deak
2024-02-20 21:18 ` [PATCH v2 06/21] drm/i915/dp: Factor out intel_dp_config_required_rate() Imre Deak
2024-02-20 21:18 ` [PATCH v2 07/21] drm/i915/dp: Export intel_dp_max_common_rate/lane_count() Imre Deak
2024-02-20 21:18 ` [PATCH v2 08/21] drm/i915/dp: Factor out intel_dp_update_sink_caps() Imre Deak
2024-02-20 21:18 ` [PATCH v2 09/21] drm/i915/dp: Factor out intel_dp_read_dprx_caps() Imre Deak
2024-02-20 21:18 ` [PATCH v2 10/21] drm/i915/dp: Add intel_dp_max_link_data_rate() Imre Deak
2024-02-20 21:18 ` [PATCH v2 11/21] drm/i915/dp: Add way to get active pipes with syncing commits Imre Deak
2024-02-23  8:10   ` Shankar, Uma
2024-02-23 21:11   ` Ville Syrjälä
2024-02-23 22:09     ` Imre Deak
2024-02-23 22:13       ` Ville Syrjälä
2024-02-26 18:52   ` [PATCH v3 11/21] drm/i915/dp: Sync instead of try-sync commits when getting active pipes Imre Deak
2024-02-20 21:18 ` [PATCH v2 12/21] drm/i915/dp: Add support for DP tunnel BW allocation Imre Deak
2024-02-23 21:37   ` Ville Syrjälä
2024-02-26 11:42     ` Imre Deak
2024-02-26 10:47   ` Shankar, Uma
2024-02-26 18:52   ` [PATCH v3 " Imre Deak
2024-02-20 21:18 ` [PATCH v2 13/21] drm/i915/dp: Add DP tunnel atomic state and check BW limit Imre Deak
2024-02-23 10:13   ` Shankar, Uma
2024-02-20 21:18 ` [PATCH v2 14/21] drm/i915/dp: Account for tunnel BW limit in intel_dp_max_link_data_rate() Imre Deak
2024-02-20 21:18 ` [PATCH v2 15/21] drm/i915/dp: Compute DP tunnel BW during encoder state computation Imre Deak
2024-02-20 21:18 ` [PATCH v2 16/21] drm/i915/dp: Allocate/free DP tunnel BW in the encoder enable/disable hooks Imre Deak
2024-02-23 21:25   ` Ville Syrjälä
2024-02-20 21:18 ` [PATCH v2 17/21] drm/i915/dp: Handle DP tunnel IRQs Imre Deak
2024-02-23 10:19   ` Shankar, Uma
2024-02-20 21:18 ` [PATCH v2 18/21] drm/i915/dp: Call intel_dp_sync_state() always for DDI DP encoders Imre Deak
2024-02-20 21:18 ` [PATCH v2 19/21] drm/i915/dp: Suspend/resume DP tunnels Imre Deak
2024-02-23 10:23   ` Shankar, Uma
2024-02-20 21:18 ` [PATCH v2 20/21] drm/i915/dp: Read DPRX for all long HPD pulses Imre Deak
2024-02-23 10:33   ` Shankar, Uma
2024-02-20 21:18 ` [PATCH v2 21/21] drm/i915/dp: Enable DP tunnel BW allocation mode Imre Deak
2024-02-23 10:36   ` Shankar, Uma
2024-02-21  1:49 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Display Port tunnel BW allocation support (rev2) Patchwork
2024-02-21  1:49 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-02-21  2:08 ` ✓ Fi.CI.BAT: success " Patchwork
2024-02-21  5:25 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-02-23 22:14 ` [PATCH v2 00/21] drm/i915: Add Display Port tunnel BW allocation support Ville Syrjälä
2024-02-26 13:54 ` Jani Nikula
2024-02-26 13:59   ` Maxime Ripard
2024-02-27  1:02 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Display Port tunnel BW allocation support (rev6) Patchwork
2024-02-27  1:02 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-02-27  1:18 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-02-27 10:59   ` Imre Deak
2024-02-27 11:34     ` Illipilli, TejasreeX
2024-02-27 11:32 ` ✓ Fi.CI.BAT: success " Patchwork
2024-02-27 14:21 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-02-27 15:51   ` Imre Deak
2024-02-28  5:55 ` ✓ Fi.CI.IGT: success " Patchwork

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