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Mon, 26 Feb 2024 10:23:26 -0800 (PST) Received: from localhost.localdomain ([113.30.217.222]) by smtp.gmail.com with ESMTPSA id v19-20020a170902d09300b001dba98889a3sm2353plv.71.2024.02.26.10.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Feb 2024 10:23:26 -0800 (PST) From: Anand Moon To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Anand Moon , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1] arm64: dts: rockchip: Add cache information to the Rockchip RK3566 and RK3568 SoC Date: Mon, 26 Feb 2024 23:53:03 +0530 Message-ID: <20240226182310.4032-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240226_102328_426639_A0EE00F0 X-CRM114-Status: GOOD ( 12.13 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org As per RK3568 Datasheet and TRM add missing cache information to the Rockchip RK3566 and RK3568 SoC. - Each Cortex-A55 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available with ECC. - Along with 512KB Unified L3 cache with ECC. With adding instruction cache and data cache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. Signed-off-by: Anand Moon --- [0] http://www.rock-chips.com/uploads/pdf/2022.8.26/191/RK3568%20Brief%20Datasheet.pdf [1] https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%20Part1%20V1.1-20210301.pdf --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index c19c0f1b3778..49235efefb6b 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -56,6 +56,13 @@ cpu0: cpu@0 { clocks = <&scmi_clk 0>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -65,6 +72,13 @@ cpu1: cpu@100 { reg = <0x0 0x100>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -74,6 +88,13 @@ cpu2: cpu@200 { reg = <0x0 0x200>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -83,8 +104,24 @@ cpu3: cpu@300 { reg = <0x0 0x300>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x7d000>; /* L3. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; + }; }; cpu0_opp_table: opp-table-0 { -- 2.43.0 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACC6EC48BF6 for ; Mon, 26 Feb 2024 18:23:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As per RK3568 Datasheet and TRM add missing cache information to the Rockchip RK3566 and RK3568 SoC. - Each Cortex-A55 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available with ECC. - Along with 512KB Unified L3 cache with ECC. With adding instruction cache and data cache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. Signed-off-by: Anand Moon --- [0] http://www.rock-chips.com/uploads/pdf/2022.8.26/191/RK3568%20Brief%20Datasheet.pdf [1] https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%20Part1%20V1.1-20210301.pdf --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index c19c0f1b3778..49235efefb6b 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -56,6 +56,13 @@ cpu0: cpu@0 { clocks = <&scmi_clk 0>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -65,6 +72,13 @@ cpu1: cpu@100 { reg = <0x0 0x100>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -74,6 +88,13 @@ cpu2: cpu@200 { reg = <0x0 0x200>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -83,8 +104,24 @@ cpu3: cpu@300 { reg = <0x0 0x300>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x7d000>; /* L3. 512 KB */ + cache-line-size = <64>; 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With adding instruction cache and data cache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. Signed-off-by: Anand Moon --- [0] http://www.rock-chips.com/uploads/pdf/2022.8.26/191/RK3568%20Brief%20Datasheet.pdf [1] https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%20Part1%20V1.1-20210301.pdf --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index c19c0f1b3778..49235efefb6b 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -56,6 +56,13 @@ cpu0: cpu@0 { clocks = <&scmi_clk 0>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -65,6 +72,13 @@ cpu1: cpu@100 { reg = <0x0 0x100>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -74,6 +88,13 @@ cpu2: cpu@200 { reg = <0x0 0x200>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -83,8 +104,24 @@ cpu3: cpu@300 { reg = <0x0 0x300>; #cooling-cells = <2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x7d000>; /* L3. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; + }; }; cpu0_opp_table: opp-table-0 { -- 2.43.0