From: Matt Roper <matthew.d.roper@intel.com>
To: Andi Shyti <andi.shyti@linux.intel.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
Chris Wilson <chris.p.wilson@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
John Harrison <John.C.Harrison@intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
<stable@vger.kernel.org>, Andi Shyti <andi.shyti@kernel.org>
Subject: Re: [PATCH v3 2/4] drm/i915/gt: Do not exposed fused off engines.
Date: Tue, 5 Mar 2024 13:52:18 -0800 [thread overview]
Message-ID: <20240305215218.GY718896@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20240229232859.70058-3-andi.shyti@linux.intel.com>
On Fri, Mar 01, 2024 at 12:28:57AM +0100, Andi Shyti wrote:
> Some of the CCS engines are disabled. They should not be listed
> in the uabi_engine list, that is the list of engines that the
> user can see.
Fused off engines already aren't visible to userspace (or to the kernel
for that matter). For CCS engines engine_mask_apply_compute_fuses()
removes the fused off engines from the runtime engine mask; other engine
types are handled in similar functions. Any engine that doesn't appear
in the filtered down engine_mask won't even have a 'struct
intel_engine_cs' allocated for it.
Matt
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Requires: 4e4f77d74878 ("drm/i915/gt: Refactor uabi engine class/instance list creation")
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index cf8f24ad88f6..ec5bcd1c1ec4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -244,6 +244,18 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
> if (uabi_class > I915_LAST_UABI_ENGINE_CLASS)
> continue;
>
> + /*
> + * If the CCS engine is fused off, the corresponding bit
> + * in the engine mask is disabled. Do not expose it
> + * to the user.
> + *
> + * By default at least one engine is enabled (check
> + * the engine_mask_apply_compute_fuses() function.
> + */
> + if (!(engine->gt->info.engine_mask &
> + BIT(_CCS(engine->uabi_instance))))
> + continue;
> +
> GEM_BUG_ON(uabi_class >=
> ARRAY_SIZE(i915->engine_uabi_class_count));
> i915->engine_uabi_class_count[uabi_class]++;
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
next prev parent reply other threads:[~2024-03-05 21:52 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-29 23:28 [PATCH v3 0/4] Disable automatic load CCS load balancing Andi Shyti
2024-02-29 23:28 ` [PATCH v3 1/4] drm/i915/gt: Refactor uabi engine class/instance list creation Andi Shyti
2024-02-29 23:29 ` kernel test robot
2024-03-05 10:14 ` Joonas Lahtinen
2024-03-05 10:18 ` Andi Shyti
2024-02-29 23:28 ` [PATCH v3 2/4] drm/i915/gt: Do not exposed fused off engines Andi Shyti
2024-03-05 21:52 ` Matt Roper [this message]
2024-02-29 23:28 ` [PATCH v3 3/4] drm/i915/gt: Disable HW load balancing for CCS Andi Shyti
2024-02-29 23:28 ` [PATCH v3 4/4] drm/i915/gt: Enable only one CCS for compute workload Andi Shyti
2024-03-01 0:11 ` ✗ Fi.CI.CHECKPATCH: warning for Disable automatic load CCS load balancing (rev4) Patchwork
2024-03-01 0:35 ` ✗ Fi.CI.BAT: failure " Patchwork
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