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From: <shaibran@amazon.com>
To: <ferruh.yigit@amd.com>
Cc: <dev@dpdk.org>, Shai Brandes <shaibran@amazon.com>
Subject: [PATCH v3 28/33] net/ena/hal: cosmetic changes
Date: Wed, 6 Mar 2024 14:24:40 +0200	[thread overview]
Message-ID: <20240306122445.4350-29-shaibran@amazon.com> (raw)
In-Reply-To: <20240306122445.4350-1-shaibran@amazon.com>

From: Shai Brandes <shaibran@amazon.com>

1. modify log prints to use correct format specifier
   for unsigned variables.
2. removed line breaks for lines that do not exceed
   maximal line length.

Signed-off-by: Shai Brandes <shaibran@amazon.com>
Reviewed-by: Amit Bernstein <amitbern@amazon.com>
---
 drivers/net/ena/hal/ena_eth_com.c   | 22 +++++++++++-----------
 drivers/net/ena/hal/ena_plat_dpdk.h |  5 ++---
 2 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/net/ena/hal/ena_eth_com.c b/drivers/net/ena/hal/ena_eth_com.c
index ebad38d15a..87a2dbfba1 100644
--- a/drivers/net/ena/hal/ena_eth_com.c
+++ b/drivers/net/ena/hal/ena_eth_com.c
@@ -64,7 +64,7 @@ static int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq,
 
 		io_sq->entries_in_tx_burst_left--;
 		ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq),
-			    "Decreasing entries_in_tx_burst_left of queue %d to %d\n",
+			    "Decreasing entries_in_tx_burst_left of queue %u to %u\n",
 			    io_sq->qid, io_sq->entries_in_tx_burst_left);
 	}
 
@@ -259,7 +259,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
 		if (unlikely((status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >>
 		    ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT && count != 0)) {
 			ena_trc_err(dev,
-				    "First bit is on in descriptor #%d on q_id: %d, req_id: %u\n",
+				    "First bit is on in descriptor #%u on q_id: %u, req_id: %u\n",
 				    count, io_cq->qid, cdesc->req_id);
 			return ENA_COM_FAULT;
 		}
@@ -268,7 +268,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
 					ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK)) &&
 			      ena_com_get_cap(dev, ENA_ADMIN_CDESC_MBZ))) {
 			ena_trc_err(dev,
-				    "Corrupted RX descriptor #%d on q_id: %d, req_id: %u\n",
+				    "Corrupted RX descriptor #%u on q_id: %u, req_id: %u\n",
 				    count, io_cq->qid, cdesc->req_id);
 			return ENA_COM_FAULT;
 		}
@@ -288,7 +288,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
 		io_cq->cur_rx_pkt_cdesc_start_idx = head_masked;
 
 		ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
-			    "ENA q_id: %d packets were completed. first desc idx %u descs# %d\n",
+			    "ENA q_id: %u packets were completed. first desc idx %u descs# %u\n",
 			    io_cq->qid, *first_cdesc_idx, count);
 	} else {
 		io_cq->cur_rx_pkt_cdesc_count = count;
@@ -394,7 +394,7 @@ static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq,
 		ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
 
 	ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
-		    "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %d frag %d cdesc_status %x\n",
+		    "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %u frag %d cdesc_status %x\n",
 		    ena_rx_ctx->l3_proto,
 		    ena_rx_ctx->l4_proto,
 		    ena_rx_ctx->l3_csum_err,
@@ -434,7 +434,7 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
 
 	if (unlikely(header_len > io_sq->tx_max_header_size)) {
 		ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
-			    "Header size is too large %d max header: %d\n",
+			    "Header size is too large %u max header: %u\n",
 			    header_len, io_sq->tx_max_header_size);
 		return ENA_COM_INVAL;
 	}
@@ -592,12 +592,12 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
 	}
 
 	ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
-		    "Fetch rx packet: queue %d completed desc: %d\n",
+		    "Fetch rx packet: queue %u completed desc: %u\n",
 		    io_cq->qid, nb_hw_desc);
 
 	if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) {
 		ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq),
-			    "Too many RX cdescs (%d) > MAX(%d)\n",
+			    "Too many RX cdescs (%u) > MAX(%u)\n",
 			    nb_hw_desc, ena_rx_ctx->max_bufs);
 		return ENA_COM_NO_SPACE;
 	}
@@ -622,7 +622,7 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
 	io_sq->next_to_comp += nb_hw_desc;
 
 	ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
-		    "[%s][QID#%d] Updating SQ head to: %d\n", __func__,
+		    "Updating Queue %u, SQ head to: %u\n",
 		    io_sq->qid, io_sq->next_to_comp);
 
 	/* Get rx flags from the last pkt */
@@ -660,8 +660,8 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 	desc->req_id = req_id;
 
 	ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq),
-		    "[%s] Adding single RX desc, Queue: %u, req_id: %u\n",
-		    __func__, io_sq->qid, req_id);
+		    "Adding single RX desc, Queue: %u, req_id: %u\n",
+		    io_sq->qid, req_id);
 
 	desc->buff_addr_lo = (u32)ena_buf->paddr;
 	desc->buff_addr_hi =
diff --git a/drivers/net/ena/hal/ena_plat_dpdk.h b/drivers/net/ena/hal/ena_plat_dpdk.h
index aa8fbb0cd9..fc602971d5 100644
--- a/drivers/net/ena/hal/ena_plat_dpdk.h
+++ b/drivers/net/ena/hal/ena_plat_dpdk.h
@@ -40,7 +40,7 @@ typedef uint64_t dma_addr_t;
 #define ETIME ETIMEDOUT
 #endif
 
-#define ENA_PRIU64 PRIu64
+#define ENA_PRIu64 PRIu64
 #define ena_atomic32_t rte_atomic32_t
 #define ena_mem_handle_t const struct rte_memzone *
 
@@ -73,8 +73,7 @@ typedef uint64_t dma_addr_t;
 /* Redefine memcpy with caution: rte_memcpy can be simply aliased to memcpy, so
  * make the redefinition only if it's safe (and beneficial) to do so.
  */
-#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64_MEMCPY) || \
-	defined(RTE_ARCH_ARM_NEON_MEMCPY)
+#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64_MEMCPY) || defined(RTE_ARCH_ARM_NEON_MEMCPY)
 #undef memcpy
 #define memcpy rte_memcpy
 #endif
-- 
2.17.1


  parent reply	other threads:[~2024-03-06 12:28 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-06 12:24 [PATCH v3 00/33] net/ena: v2.9.0 driver release shaibran
2024-03-06 12:24 ` [PATCH v3 01/33] net/ena: rework the metrics multi-process functions shaibran
2024-03-06 12:24 ` [PATCH v3 02/33] net/ena: report new supported link speed capabilities shaibran
2024-03-06 12:24 ` [PATCH v3 03/33] net/ena: update imissed stat with Rx overruns shaibran
2024-03-06 12:24 ` [PATCH v3 04/33] net/ena: sub-optimal configuration notifications support shaibran
2024-03-08 17:23   ` Ferruh Yigit
2024-03-10 14:43     ` Brandes, Shai
2024-03-13 11:18       ` Ferruh Yigit
2024-03-06 12:24 ` [PATCH v3 05/33] net/ena: fix fast mbuf free shaibran
2024-03-08 17:23   ` Ferruh Yigit
2024-03-10 14:58     ` Brandes, Shai
2024-03-13 11:28       ` Ferruh Yigit
2024-03-06 12:24 ` [PATCH v3 06/33] net/ena: rename base folder to hal shaibran
2024-03-08 17:23   ` Ferruh Yigit
2024-03-10 14:23     ` Brandes, Shai
2024-03-06 12:24 ` [PATCH v3 07/33] net/ena: restructure the llq policy setting process shaibran
2024-03-08 17:24   ` Ferruh Yigit
2024-03-10 14:29     ` Brandes, Shai
2024-03-13 11:21       ` Ferruh Yigit
2024-03-06 12:24 ` [PATCH v3 08/33] net/ena/hal: exponential backoff exp limit shaibran
2024-03-08 17:24   ` Ferruh Yigit
2024-03-10 14:53     ` Brandes, Shai
2024-03-12 16:53       ` Brandes, Shai
2024-03-13 11:25         ` Ferruh Yigit
2024-03-06 12:24 ` [PATCH v3 09/33] net/ena/hal: add a new csum offload bit shaibran
2024-03-08 17:24   ` Ferruh Yigit
2024-03-06 12:24 ` [PATCH v3 10/33] net/ena/hal: added a bus parameter to ena memcpy macro shaibran
2024-03-08 17:25   ` Ferruh Yigit
2024-03-10 15:08     ` Brandes, Shai
2024-03-13 11:27       ` Ferruh Yigit
2024-03-06 12:24 ` [PATCH v3 11/33] net/ena/hal: optimize Rx ring submission queue shaibran
2024-03-06 12:24 ` [PATCH v3 12/33] net/ena/hal: rename fields in completion descriptors shaibran
2024-03-06 12:24 ` [PATCH v3 13/33] net/ena/hal: use correct read once on u8 field shaibran
2024-03-06 12:24 ` [PATCH v3 14/33] net/ena/hal: add completion descriptor corruption check shaibran
2024-03-06 12:24 ` [PATCH v3 15/33] net/ena/hal: malformed Tx descriptor error reason shaibran
2024-03-06 12:24 ` [PATCH v3 16/33] net/ena/hal: phc feature modifications shaibran
2024-03-06 12:24 ` [PATCH v3 17/33] net/ena/hal: restructure interrupt handling shaibran
2024-03-06 12:24 ` [PATCH v3 18/33] net/ena/hal: add unlikely to error checks shaibran
2024-03-06 12:24 ` [PATCH v3 19/33] net/ena/hal: missing admin interrupt reset reason shaibran
2024-03-06 12:24 ` [PATCH v3 20/33] net/ena/hal: check for existing keep alive notification shaibran
2024-03-06 12:24 ` [PATCH v3 21/33] net/ena/hal: modify memory barrier comment shaibran
2024-03-06 12:24 ` [PATCH v3 22/33] net/ena/hal: rework Rx ring submission queue shaibran
2024-03-06 12:24 ` [PATCH v3 23/33] net/ena/hal: remove operating system type enum shaibran
2024-03-06 12:24 ` [PATCH v3 24/33] net/ena/hal: handle command abort shaibran
2024-03-06 12:24 ` [PATCH v3 25/33] net/ena/hal: add support for device reset request shaibran
2024-03-06 12:24 ` [PATCH v3 26/33] net/ena: cosmetic changes shaibran
2024-03-08 11:17   ` Ferruh Yigit
2024-03-08 13:19     ` Brandes, Shai
2024-03-08 14:50       ` Ferruh Yigit
2024-03-06 12:24 ` [PATCH v3 27/33] net/ena/hal: modify customer metrics memory management shaibran
2024-03-06 12:24 ` shaibran [this message]
2024-03-08 17:43   ` [PATCH v3 28/33] net/ena/hal: cosmetic changes Ferruh Yigit
2024-03-08 17:44     ` Ferruh Yigit
2024-03-12 17:12       ` Brandes, Shai
2024-03-06 12:24 ` [PATCH v3 29/33] net/ena: update device-preferred size of rings shaibran
2024-03-06 12:24 ` [PATCH v3 30/33] net/ena: exhaust interrupt callbacks in device close shaibran
2024-03-06 12:24 ` [PATCH v3 31/33] net/ena: support max large llq depth from the device shaibran
2024-03-06 12:24 ` [PATCH v3 32/33] net/ena: control path pure polling mode shaibran
2024-03-06 12:24 ` [PATCH v3 33/33] net/ena: upgrade driver version to 2.9.0 shaibran
2024-03-08 17:36 ` [PATCH v3 00/33] net/ena: v2.9.0 driver release Ferruh Yigit
2024-03-08 20:26   ` Brandes, Shai
2024-03-10 14:21     ` Brandes, Shai
2024-03-13 11:28       ` Ferruh Yigit
2024-03-13 13:38         ` Brandes, Shai

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