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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id l15-20020a5d526f000000b0033e7a102cfesm12286150wrc.64.2024.03.13.12.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 12:13:36 -0700 (PDT) Date: Wed, 13 Mar 2024 20:13:34 +0100 From: Andrew Jones To: Himanshu Chauhan Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v5 2/3] target/riscv: Expose sdtrig ISA extension Message-ID: <20240313-e296698984d8f6fc914169a2@orel> References: <20240313182009.608685-1-hchauhan@ventanamicro.com> <20240313182009.608685-3-hchauhan@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240313182009.608685-3-hchauhan@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Wed, Mar 13, 2024 at 11:50:08PM +0530, Himanshu Chauhan wrote: > This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled. > The sdtrig extension may or may not be implemented in a system. Therefore, the > -cpu rv64,sdtrig= > option can be used to dynamically turn sdtrig extension on or off. > > Since, the sdtrig ISA extension is a superset of debug specification, disable > the debug property when sdtrig is enabled. A warning is printed when this is > done. > > By default, the sdtrig extension is disabled and debug property enabled as usual. > > Signed-off-by: Himanshu Chauhan > --- > target/riscv/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 2602aae9f5..e0710010f5 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -175,6 +175,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > @@ -1008,6 +1009,10 @@ static void riscv_cpu_reset_hold(Object *obj) > set_default_nan_mode(1, &env->fp_status); > > #ifndef CONFIG_USER_ONLY > + if (!cpu->cfg.debug && cpu->cfg.ext_sdtrig) { > + cpu->cfg.debug = 1; nit: '= true' I also wonder if we need a warning here that says something like "reenabling 'debug' since 'sdtrig' is enabled...", since the only way we'd get here is if the user did 'debug=off,sdtrig=on'. But, I think I might be OK with just silently ignoring that 'debug=off' too. Thanks, drew > + } > + > if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { > riscv_trigger_reset_hold(env); > } > @@ -1480,6 +1485,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), > MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), > > + MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, false), > MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), > MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), > MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), > -- > 2.34.1 > >