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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id f12-20020a05640214cc00b00568a22038b4sm649547edx.88.2024.03.14.10.13.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 10:13:20 -0700 (PDT) Date: Thu, 14 Mar 2024 18:13:19 +0100 From: Andrew Jones To: Himanshu Chauhan Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v6 3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Message-ID: <20240314-00815f922c7320ceca28398b@orel> References: <20240314113510.477862-1-hchauhan@ventanamicro.com> <20240314113510.477862-4-hchauhan@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240314113510.477862-4-hchauhan@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Thu, Mar 14, 2024 at 05:05:10PM +0530, Himanshu Chauhan wrote: > Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable > the sdtrig extension and disable the debug property for these CPUs. The commit message needs to be updated to remove the 'and disable the debug property'. > > Signed-off-by: Himanshu Chauhan > --- > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 66c91fffd6..3c7ad1c903 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -569,6 +569,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) > cpu->cfg.cbom_blocksize = 64; > cpu->cfg.cboz_blocksize = 64; > cpu->cfg.ext_zicboz = true; > + cpu->cfg.ext_sdtrig = true; > cpu->cfg.ext_smaia = true; > cpu->cfg.ext_ssaia = true; > cpu->cfg.ext_sscofpmf = true; > -- > 2.34.1 > Thanks, drew