From: Himanshu Chauhan <hchauhan@ventanamicro.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: ajones@ventanamicro.com
Subject: [PATCH v6 2/3] target/riscv: Expose sdtrig ISA extension
Date: Thu, 14 Mar 2024 17:05:09 +0530 [thread overview]
Message-ID: <20240314113510.477862-3-hchauhan@ventanamicro.com> (raw)
In-Reply-To: <20240314113510.477862-1-hchauhan@ventanamicro.com>
This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled.
The sdtrig extension may or may not be implemented in a system. Therefore, the
-cpu rv64,sdtrig=<true/false>
option can be used to dynamically turn sdtrig extension on or off.
Since, the sdtrig ISA extension is a superset of debug specification, disable
the debug property when sdtrig is enabled. A warning is printed when this is
done.
By default, the sdtrig extension is disabled and debug property enabled as usual.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
---
target/riscv/cpu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2602aae9f5..66c91fffd6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -175,6 +175,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
+ ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
@@ -1008,6 +1009,11 @@ static void riscv_cpu_reset_hold(Object *obj)
set_default_nan_mode(1, &env->fp_status);
#ifndef CONFIG_USER_ONLY
+ if (!cpu->cfg.debug && cpu->cfg.ext_sdtrig) {
+ warn_report("Enabling 'debug' since 'sdtrig' is enabled.");
+ cpu->cfg.debug = true;
+ }
+
if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) {
riscv_trigger_reset_hold(env);
}
@@ -1480,6 +1486,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false),
MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
+ MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, false),
MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
--
2.34.1
next prev parent reply other threads:[~2024-03-14 11:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 11:35 [PATCH v6 0/3] Introduce sdtrig ISA extension Himanshu Chauhan
2024-03-14 11:35 ` [PATCH v6 1/3] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Himanshu Chauhan
2024-03-14 17:07 ` Andrew Jones
2024-03-14 11:35 ` Himanshu Chauhan [this message]
2024-03-14 17:12 ` [PATCH v6 2/3] target/riscv: Expose sdtrig ISA extension Andrew Jones
2024-03-14 11:35 ` [PATCH v6 3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Himanshu Chauhan
2024-03-14 17:13 ` Andrew Jones
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240314113510.477862-3-hchauhan@ventanamicro.com \
--to=hchauhan@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.