From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-s390x@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org,
"Anton Johansson" <anjo@rev.ng>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Max Filippov" <jcmvbkbc@gmail.com>
Subject: [PATCH-for-9.1 26/27] target/xtensa: Convert to TCGCPUOps::get_cpu_state()
Date: Tue, 19 Mar 2024 16:42:55 +0100 [thread overview]
Message-ID: <20240319154258.71206-27-philmd@linaro.org> (raw)
In-Reply-To: <20240319154258.71206-1-philmd@linaro.org>
Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/xtensa/cpu.h | 70 ---------------------------------------------
target/xtensa/cpu.c | 69 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 69 insertions(+), 70 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 3826b779e4..2b6f2bdea7 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -734,76 +734,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
#include "exec/cpu-all.h"
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = 0;
- *flags |= xtensa_get_ring(env);
- if (env->sregs[PS] & PS_EXCM) {
- *flags |= XTENSA_TBFLAG_EXCM;
- } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
- target_ulong lend_dist =
- env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
-
- /*
- * 0 in the csbase_lend field means that there may not be a loopback
- * for any instruction that starts inside this page. Any other value
- * means that an instruction that ends at this offset from the page
- * start may loop back and will need loopback code to be generated.
- *
- * lend_dist is 0 when LEND points to the start of the page, but
- * no instruction that starts inside this page may end at offset 0,
- * so it's still correct.
- *
- * When an instruction ends at a page boundary it may only start in
- * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
- * for the TB that contains this instruction.
- */
- if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
- target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
-
- *cs_base = lend_dist;
- if (lbeg_off < 256) {
- *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
- }
- }
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
- (env->sregs[LITBASE] & 1)) {
- *flags |= XTENSA_TBFLAG_LITBASE;
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
- if (xtensa_get_cintlevel(env) < env->config->debug_level) {
- *flags |= XTENSA_TBFLAG_DEBUG;
- }
- if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
- *flags |= XTENSA_TBFLAG_ICOUNT;
- }
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
- *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
- (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
- uint32_t windowstart = xtensa_replicate_windowstart(env) >>
- (env->sregs[WINDOW_BASE] + 1);
- uint32_t w = ctz32(windowstart | 0x8);
-
- *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
- *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
- PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
- } else {
- *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
- }
- if (env->yield_needed) {
- *flags |= XTENSA_TBFLAG_YIELD;
- }
-}
-
XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type,
Clock *cpu_refclk);
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 875cf843c9..35c66432a1 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -63,6 +63,74 @@ static void xtensa_restore_state_to_opc(CPUState *cs,
cpu->env.pc = data[0];
}
+static void xtensa_get_cpu_state(CPUXtensaState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = 0;
+ *flags |= xtensa_get_ring(env);
+ if (env->sregs[PS] & PS_EXCM) {
+ *flags |= XTENSA_TBFLAG_EXCM;
+ } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
+ target_ulong lend_dist =
+ env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
+
+ /*
+ * 0 in the csbase_lend field means that there may not be a loopback
+ * for any instruction that starts inside this page. Any other value
+ * means that an instruction that ends at this offset from the page
+ * start may loop back and will need loopback code to be generated.
+ *
+ * lend_dist is 0 when LEND points to the start of the page, but
+ * no instruction that starts inside this page may end at offset 0,
+ * so it's still correct.
+ *
+ * When an instruction ends at a page boundary it may only start in
+ * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
+ * for the TB that contains this instruction.
+ */
+ if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
+ target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
+
+ *cs_base = lend_dist;
+ if (lbeg_off < 256) {
+ *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
+ }
+ }
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
+ (env->sregs[LITBASE] & 1)) {
+ *flags |= XTENSA_TBFLAG_LITBASE;
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
+ if (xtensa_get_cintlevel(env) < env->config->debug_level) {
+ *flags |= XTENSA_TBFLAG_DEBUG;
+ }
+ if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
+ *flags |= XTENSA_TBFLAG_ICOUNT;
+ }
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
+ *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
+ (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
+ uint32_t windowstart = xtensa_replicate_windowstart(env) >>
+ (env->sregs[WINDOW_BASE] + 1);
+ uint32_t w = ctz32(windowstart | 0x8);
+
+ *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
+ *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
+ PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
+ } else {
+ *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
+ }
+ if (env->yield_needed) {
+ *flags |= XTENSA_TBFLAG_YIELD;
+ }
+}
+
static bool xtensa_cpu_has_work(CPUState *cs)
{
#ifndef CONFIG_USER_ONLY
@@ -230,6 +298,7 @@ static const TCGCPUOps xtensa_tcg_ops = {
.initialize = xtensa_translate_init,
.debug_excp_handler = xtensa_breakpoint_handler,
.restore_state_to_opc = xtensa_restore_state_to_opc,
+ .get_cpu_state = xtensa_get_cpu_state,
#ifndef CONFIG_USER_ONLY
.tlb_fill = xtensa_cpu_tlb_fill,
--
2.41.0
next prev parent reply other threads:[~2024-03-19 15:47 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-19 15:42 [PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 01/27] accel/tcg: Ensure frontends define restore_state_to_opc handler Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 02/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 03/27] target/alpha: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 04/27] target/arm: Restrict TCG-specific declarations Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 05/27] target/arm: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 06/27] target/avr: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 07/27] target/cris: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 08/27] target/hexagon: " Philippe Mathieu-Daudé
2024-03-22 15:44 ` Brian Cain
2024-03-19 15:42 ` [PATCH-for-9.1 09/27] target/hppa: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 10/27] target/i386: " Philippe Mathieu-Daudé
2024-03-19 21:01 ` Richard Henderson
2024-03-19 15:42 ` [PATCH-for-9.1 11/27] target/loongarch: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 12/27] target/m68k: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 13/27] target/microblaze: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 14/27] target/mips: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 15/27] target/nios2: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 16/27] target/openrisc: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 17/27] target/ppc: Indent ppc_tcg_ops[] with 4 spaces Philippe Mathieu-Daudé
2024-03-20 4:49 ` Nicholas Piggin
2024-03-19 15:42 ` [PATCH-for-9.1 18/27] target/ppc: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-20 5:00 ` Nicholas Piggin
2024-03-19 15:42 ` [PATCH-for-9.1 19/27] target/riscv: " Philippe Mathieu-Daudé
2024-03-19 21:26 ` Daniel Henrique Barboza
2024-03-19 15:42 ` [PATCH-for-9.1 20/27] target/rx: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 21/27] target/s390x: Restrict TCG-specific declarations Philippe Mathieu-Daudé
2024-03-20 6:38 ` Thomas Huth
2024-03-19 15:42 ` [PATCH-for-9.1 22/27] target/s390x: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-19 21:05 ` Richard Henderson
2024-03-20 7:09 ` Philippe Mathieu-Daudé
2024-03-21 2:20 ` Richard Henderson
2024-03-19 15:42 ` [PATCH-for-9.1 23/27] target/sh4: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 24/27] target/sparc: " Philippe Mathieu-Daudé
2024-03-19 21:14 ` Richard Henderson
2024-03-19 15:42 ` [PATCH-for-9.1 25/27] target/tricore: " Philippe Mathieu-Daudé
2024-03-24 9:44 ` Bastian Koppelmann
2024-03-19 15:42 ` Philippe Mathieu-Daudé [this message]
2024-03-19 15:42 ` [PATCH-for-9.1 27/27] accel/tcg: Remove check on TARGET_HAS_CPU_GET_TB_CPU_STATE Philippe Mathieu-Daudé
2024-03-19 15:48 ` [PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler Philippe Mathieu-Daudé
2024-03-19 16:01 ` Claudio Fontana
2024-03-19 21:16 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240319154258.71206-27-philmd@linaro.org \
--to=philmd@linaro.org \
--cc=anjo@rev.ng \
--cc=jcmvbkbc@gmail.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=qemu-s390x@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.