From: Minwoo Im <minwoo.im.dev@gmail.com>
To: Klaus Jensen <its@irrelevant.dk>, Keith Busch <kbusch@kernel.org>
Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org,
Minwoo Im <minwoo.im@samsung.com>
Subject: [PATCH v2 2/4] hw/nvme: separate identify data for sec. ctrl list
Date: Mon, 1 Apr 2024 04:30:30 +0900 [thread overview]
Message-ID: <20240331193032.5186-3-minwoo.im.dev@gmail.com> (raw)
In-Reply-To: <20240331193032.5186-1-minwoo.im.dev@gmail.com>
From: Minwoo Im <minwoo.im@samsung.com>
Secondary controller list for virtualization has been managed by
Identify Secondary Controller List data structure with NvmeSecCtrlList
where up to 127 secondary controller entries can be managed. The
problem hasn't arisen so far because NVME_MAX_VFS has been 127.
This patch separated identify data itself from the actual secondary
controller list managed by controller to support more than 127 secondary
controllers with the following patch. This patch reused
NvmeSecCtrlEntry structure to manage all the possible secondary
controllers, and copy entries to identify data structure when the
command comes in.
Signed-off-by: Minwoo Im <minwoo.im@samsung.com>
---
hw/nvme/ctrl.c | 21 ++++++++++-----------
hw/nvme/nvme.h | 14 ++++++++------
hw/nvme/subsys.c | 8 ++++----
3 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index cfe53a358871..7e60bc9f2075 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -219,7 +219,6 @@
#define NVME_TEMPERATURE_CRITICAL 0x175
#define NVME_NUM_FW_SLOTS 1
#define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB)
-#define NVME_MAX_VFS 127
#define NVME_VF_RES_GRANULARITY 1
#define NVME_VF_OFFSET 0x1
#define NVME_VF_STRIDE 1
@@ -5480,14 +5479,14 @@ static uint16_t nvme_identify_sec_ctrl_list(NvmeCtrl *n, NvmeRequest *req)
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
uint16_t pri_ctrl_id = le16_to_cpu(n->pri_ctrl_cap.cntlid);
uint16_t min_id = le16_to_cpu(c->ctrlid);
- uint8_t num_sec_ctrl = n->sec_ctrl_list.numcntl;
+ uint8_t num_sec_ctrl = n->nr_sec_ctrls;
NvmeSecCtrlList list = {0};
uint8_t i;
for (i = 0; i < num_sec_ctrl; i++) {
- if (n->sec_ctrl_list.sec[i].scid >= min_id) {
- list.numcntl = num_sec_ctrl - i;
- memcpy(&list.sec, n->sec_ctrl_list.sec + i,
+ if (n->sec_ctrl_list[i].scid >= min_id) {
+ list.numcntl = MIN(num_sec_ctrl - i, 127);
+ memcpy(&list.sec, n->sec_ctrl_list + i,
list.numcntl * sizeof(NvmeSecCtrlEntry));
break;
}
@@ -7132,8 +7131,8 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst)
if (n->params.sriov_max_vfs) {
if (!pci_is_vf(pci_dev)) {
- for (i = 0; i < n->sec_ctrl_list.numcntl; i++) {
- sctrl = &n->sec_ctrl_list.sec[i];
+ for (i = 0; i < n->nr_sec_ctrls; i++) {
+ sctrl = &n->sec_ctrl_list[i];
nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false);
}
@@ -7921,7 +7920,7 @@ static bool nvme_check_params(NvmeCtrl *n, Error **errp)
static void nvme_init_state(NvmeCtrl *n)
{
NvmePriCtrlCap *cap = &n->pri_ctrl_cap;
- NvmeSecCtrlList *list = &n->sec_ctrl_list;
+ NvmeSecCtrlEntry *list = n->sec_ctrl_list;
NvmeSecCtrlEntry *sctrl;
PCIDevice *pci = PCI_DEVICE(n);
uint8_t max_vfs;
@@ -7946,9 +7945,9 @@ static void nvme_init_state(NvmeCtrl *n)
n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1);
QTAILQ_INIT(&n->aer_queue);
- list->numcntl = cpu_to_le16(max_vfs);
+ n->nr_sec_ctrls = max_vfs;
for (i = 0; i < max_vfs; i++) {
- sctrl = &list->sec[i];
+ sctrl = &list[i];
sctrl->pcid = cpu_to_le16(n->cntlid);
sctrl->vfn = cpu_to_le16(i + 1);
}
@@ -8505,7 +8504,7 @@ static void nvme_sriov_pre_write_ctrl(PCIDevice *dev, uint32_t address,
if (!(val & PCI_SRIOV_CTRL_VFE)) {
num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF);
for (i = 0; i < num_vfs; i++) {
- sctrl = &n->sec_ctrl_list.sec[i];
+ sctrl = &n->sec_ctrl_list[i];
nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false);
}
}
diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h
index 5f2ae7b28b9c..02c11d909cd1 100644
--- a/hw/nvme/nvme.h
+++ b/hw/nvme/nvme.h
@@ -26,6 +26,7 @@
#define NVME_MAX_CONTROLLERS 256
#define NVME_MAX_NAMESPACES 256
+#define NVME_MAX_VFS 127
#define NVME_EUI64_DEFAULT ((uint64_t)0x5254000000000000)
#define NVME_FDP_MAX_EVENTS 63
#define NVME_FDP_MAXPIDS 128
@@ -597,7 +598,8 @@ typedef struct NvmeCtrl {
} features;
NvmePriCtrlCap pri_ctrl_cap;
- NvmeSecCtrlList sec_ctrl_list;
+ uint32_t nr_sec_ctrls;
+ NvmeSecCtrlEntry sec_ctrl_list[NVME_MAX_VFS];
struct {
uint16_t vqrfap;
uint16_t virfap;
@@ -647,7 +649,7 @@ static inline NvmeSecCtrlEntry *nvme_sctrl(NvmeCtrl *n)
NvmeCtrl *pf = NVME(pcie_sriov_get_pf(pci_dev));
if (pci_is_vf(pci_dev)) {
- return &pf->sec_ctrl_list.sec[pcie_sriov_vf_number(pci_dev)];
+ return &pf->sec_ctrl_list[pcie_sriov_vf_number(pci_dev)];
}
return NULL;
@@ -656,12 +658,12 @@ static inline NvmeSecCtrlEntry *nvme_sctrl(NvmeCtrl *n)
static inline NvmeSecCtrlEntry *nvme_sctrl_for_cntlid(NvmeCtrl *n,
uint16_t cntlid)
{
- NvmeSecCtrlList *list = &n->sec_ctrl_list;
+ NvmeSecCtrlEntry *list = n->sec_ctrl_list;
uint8_t i;
- for (i = 0; i < list->numcntl; i++) {
- if (le16_to_cpu(list->sec[i].scid) == cntlid) {
- return &list->sec[i];
+ for (i = 0; i < n->nr_sec_ctrls; i++) {
+ if (le16_to_cpu(list[i].scid) == cntlid) {
+ return &list[i];
}
}
diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c
index d30bb8bfd5b4..561ed04a5317 100644
--- a/hw/nvme/subsys.c
+++ b/hw/nvme/subsys.c
@@ -17,13 +17,13 @@
static int nvme_subsys_reserve_cntlids(NvmeCtrl *n, int start, int num)
{
NvmeSubsystem *subsys = n->subsys;
- NvmeSecCtrlList *list = &n->sec_ctrl_list;
+ NvmeSecCtrlEntry *list = n->sec_ctrl_list;
NvmeSecCtrlEntry *sctrl;
int i, cnt = 0;
for (i = start; i < ARRAY_SIZE(subsys->ctrls) && cnt < num; i++) {
if (!subsys->ctrls[i]) {
- sctrl = &list->sec[cnt];
+ sctrl = &list[cnt];
sctrl->scid = cpu_to_le16(i);
subsys->ctrls[i] = SUBSYS_SLOT_RSVD;
cnt++;
@@ -36,12 +36,12 @@ static int nvme_subsys_reserve_cntlids(NvmeCtrl *n, int start, int num)
static void nvme_subsys_unreserve_cntlids(NvmeCtrl *n)
{
NvmeSubsystem *subsys = n->subsys;
- NvmeSecCtrlList *list = &n->sec_ctrl_list;
+ NvmeSecCtrlEntry *list = n->sec_ctrl_list;
NvmeSecCtrlEntry *sctrl;
int i, cntlid;
for (i = 0; i < n->params.sriov_max_vfs; i++) {
- sctrl = &list->sec[i];
+ sctrl = &list[i];
cntlid = le16_to_cpu(sctrl->scid);
if (cntlid) {
--
2.34.1
next prev parent reply other threads:[~2024-03-31 19:31 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-31 19:30 [PATCH v2 0/4] hw/nvme: FDP and SR-IOV enhancements Minwoo Im
2024-03-31 19:30 ` [PATCH v2 1/4] hw/nvme: add Identify Endurance Group List Minwoo Im
2024-03-31 19:30 ` Minwoo Im [this message]
2024-03-31 19:30 ` [PATCH v2 3/4] hw/nvme: Support SR-IOV VFs more than 127 Minwoo Im
2024-05-01 12:46 ` Klaus Jensen
2024-05-07 20:48 ` Minwoo Im
2024-03-31 19:30 ` [PATCH v2 4/4] hw/nvme: Expand VI/VQ resource to uint32 Minwoo Im
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