From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Cc: <dave@stgolabs.net>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dan.j.williams@intel.com>,
<jim.harris@samsung.com>, <linux-cxl@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] cxl/core/hdm: rename interleave_mask to ig_cap_mask
Date: Wed, 3 Apr 2024 15:06:11 +0100 [thread overview]
Message-ID: <20240403150611.0000180c@Huawei.com> (raw)
In-Reply-To: <20240403021747.17260-2-yaoxt.fnst@fujitsu.com>
On Tue, 2 Apr 2024 22:17:46 -0400
Yao Xingtao <yaoxt.fnst@fujitsu.com> wrote:
> Since interleave contains interleave ways and interleave granularity,
> using ig_cap_mask is better to describe this capability.
Hi Yao,
I don't follow the reasoning of this.
ig suggests interleave granularity which whilst related to the address
bits, they aren't masking the granularity as such.
I agree current naming isn't particularly meaningful, but don't see the
suggested change as an improvement.
Jonathan
>
> Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
> ---
> drivers/cxl/core/hdm.c | 4 ++--
> drivers/cxl/cxlmem.h | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 7d97790b893d..9bb6a256cc6f 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -76,9 +76,9 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
> cxlhdm->target_count =
> FIELD_GET(CXL_HDM_DECODER_TARGET_COUNT_MASK, hdm_cap);
> if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_11_8, hdm_cap))
> - cxlhdm->interleave_mask |= GENMASK(11, 8);
> + cxlhdm->ig_cap_mask |= GENMASK(11, 8);
> if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap))
> - cxlhdm->interleave_mask |= GENMASK(14, 12);
> + cxlhdm->ig_cap_mask |= GENMASK(14, 12);
> }
>
> static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 20fb3b35e89e..b53f7ae0fdd6 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -852,7 +852,7 @@ struct cxl_hdm {
> struct cxl_component_regs regs;
> unsigned int decoder_count;
> unsigned int target_count;
> - unsigned int interleave_mask;
> + unsigned int ig_cap_mask;
> struct cxl_port *port;
> };
>
next prev parent reply other threads:[~2024-04-03 14:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-03 2:17 [PATCH v2 0/2] cxl: add interleave capability check Yao Xingtao
2024-04-03 2:17 ` [PATCH v2 1/2] cxl/core/hdm: rename interleave_mask to ig_cap_mask Yao Xingtao
2024-04-03 14:06 ` Jonathan Cameron [this message]
2024-04-08 2:42 ` Xingtao Yao (Fujitsu)
2024-04-03 2:17 ` [PATCH v2 2/2] cxl/core/region: check interleave capability Yao Xingtao
2024-04-03 14:27 ` Jonathan Cameron
2024-04-08 2:50 ` Xingtao Yao (Fujitsu)
2024-04-08 23:10 ` Dan Williams
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