From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Jones Date: Thu, 4 Apr 2024 12:57:34 +0200 Subject: [PATCH v5 02/22] RISC-V: Add FIRMWARE_READ_HI definition In-Reply-To: <20240403080452.1007601-3-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> <20240403080452.1007601-3-atishp@rivosinc.com> Message-ID: <20240404-6fc14e149cd82bb0ee8f088c@orel> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Wed, Apr 03, 2024 at 01:04:31AM -0700, Atish Patra wrote: > SBI v2.0 added another function to SBI PMU extension to read > the upper bits of a counter with width larger than XLEN. > > Add the definition for that function. > > Reviewed-by: Cl?ment L?ger > Acked-by: Conor Dooley > Reviewed-by: Anup Patel > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/sbi.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index 6e68f8dff76b..ef8311dafb91 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid { > SBI_EXT_PMU_COUNTER_START, > SBI_EXT_PMU_COUNTER_STOP, > SBI_EXT_PMU_COUNTER_FW_READ, > + SBI_EXT_PMU_COUNTER_FW_READ_HI, > }; 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charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240403080452.1007601-3-atishp@rivosinc.com> On Wed, Apr 03, 2024 at 01:04:31AM -0700, Atish Patra wrote: > SBI v2.0 added another function to SBI PMU extension to read > the upper bits of a counter with width larger than XLEN. > > Add the definition for that function. > > Reviewed-by: Clément Léger > Acked-by: Conor Dooley > Reviewed-by: Anup Patel > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/sbi.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index 6e68f8dff76b..ef8311dafb91 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid { > SBI_EXT_PMU_COUNTER_START, > SBI_EXT_PMU_COUNTER_STOP, > SBI_EXT_PMU_COUNTER_FW_READ, > + SBI_EXT_PMU_COUNTER_FW_READ_HI, > }; > > union sbi_pmu_ctr_info { > -- > 2.34.1 > Reviewed-by: Andrew Jones From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 680E8CD1284 for ; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id bo15-20020a056000068f00b003434c6d9916sm11436771wrb.110.2024.04.04.03.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Apr 2024 03:57:35 -0700 (PDT) Date: Thu, 4 Apr 2024 12:57:34 +0200 From: Andrew Jones To: Atish Patra Cc: linux-kernel@vger.kernel.org, =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Conor Dooley , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: Re: [PATCH v5 02/22] RISC-V: Add FIRMWARE_READ_HI definition Message-ID: <20240404-6fc14e149cd82bb0ee8f088c@orel> References: <20240403080452.1007601-1-atishp@rivosinc.com> <20240403080452.1007601-3-atishp@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240403080452.1007601-3-atishp@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240404_035738_844996_56B90A9B X-CRM114-Status: GOOD ( 14.08 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Apr 03, 2024 at 01:04:31AM -0700, Atish Patra wrote: > SBI v2.0 added another function to SBI PMU extension to read > the upper bits of a counter with width larger than XLEN. > = > Add the definition for that function. > = > Reviewed-by: Cl=E9ment L=E9ger > Acked-by: Conor Dooley > Reviewed-by: Anup Patel > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/sbi.h | 1 + > 1 file changed, 1 insertion(+) > = > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index 6e68f8dff76b..ef8311dafb91 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid { > SBI_EXT_PMU_COUNTER_START, > SBI_EXT_PMU_COUNTER_STOP, > SBI_EXT_PMU_COUNTER_FW_READ, > + SBI_EXT_PMU_COUNTER_FW_READ_HI, > }; > = > union sbi_pmu_ctr_info { > -- = > 2.34.1 > Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv