From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Jones Date: Thu, 4 Apr 2024 13:08:11 +0200 Subject: [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations In-Reply-To: <20240403080452.1007601-5-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> <20240403080452.1007601-5-atishp@rivosinc.com> Message-ID: <20240404-9a84f2090d00f6b994e1de7c@orel> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Wed, Apr 03, 2024 at 01:04:33AM -0700, Atish Patra wrote: > It is a good practice to use BIT() instead of (1UL << x). (1UL << x) isn't generally a problem. The problem is with (1 << x). > Replace the current usages with BIT(). > > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/sbi.h | 20 ++++++++++---------- > drivers/perf/riscv_pmu_sbi.c | 2 +- > 2 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index ef8311dafb91..4afa2cd01bae 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -233,20 +233,20 @@ enum sbi_pmu_ctr_type { > #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF > > /* Flags defined for config matching function */ > -#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) > -#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) > -#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) > -#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) > -#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) > -#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) > -#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) > -#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) > +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) > +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) > +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) > +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) > +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) > +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) > +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) > +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) > > /* Flags defined for counter start function */ > -#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) > +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) > > /* Flags defined for counter stop function */ > -#define SBI_PMU_STOP_FLAG_RESET (1 << 0) > +#define SBI_PMU_STOP_FLAG_RESET BIT(0) > > enum sbi_ext_dbcn_fid { > SBI_EXT_DBCN_CONSOLE_WRITE = 0, > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index babf1b9a4dbe..a83ae82301e3 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -386,7 +386,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) > cmask = 1; > } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) { > cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; > - cmask = 1UL << (CSR_INSTRET - CSR_CYCLE); > + cmask = BIT(CSR_INSTRET - CSR_CYCLE); > } > } > > -- > 2.34.1 > Other than the commit message, Reviewed-by: Andrew Jones Thanks, drew From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED74680BF7 for ; Thu, 4 Apr 2024 11:08:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712228896; cv=none; b=j8kBK4RjksC1l7Q8sbG3SwGE2Ab2tS3MtXJSqjBp+i4CtsjvwwTtH57z5KcYGi1PV6Ht9kN++KyMR01fZ1CAkdA3JOhhYqp7q6dXs2Uiez0TEs50cVhkiGzoljgUzsoxaqqMWFkEIZSv+IhvakCsyYAWOCo3rIq9xR45q8rgI1Y= ARC-Message-Signature:i=1; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id xh12-20020a170906da8c00b00a4e579ce949sm6017903ejb.51.2024.04.04.04.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Apr 2024 04:08:12 -0700 (PDT) Date: Thu, 4 Apr 2024 13:08:11 +0200 From: Andrew Jones To: Atish Patra Cc: linux-kernel@vger.kernel.org, Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: Re: [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Message-ID: <20240404-9a84f2090d00f6b994e1de7c@orel> References: <20240403080452.1007601-1-atishp@rivosinc.com> <20240403080452.1007601-5-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240403080452.1007601-5-atishp@rivosinc.com> On Wed, Apr 03, 2024 at 01:04:33AM -0700, Atish Patra wrote: > It is a good practice to use BIT() instead of (1UL << x). (1UL << x) isn't generally a problem. The problem is with (1 << x). > Replace the current usages with BIT(). > > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/sbi.h | 20 ++++++++++---------- > drivers/perf/riscv_pmu_sbi.c | 2 +- > 2 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index ef8311dafb91..4afa2cd01bae 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -233,20 +233,20 @@ enum sbi_pmu_ctr_type { > #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF > > /* Flags defined for config matching function */ > -#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) > -#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) > -#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) > -#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) > -#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) > -#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) > -#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) > -#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) > +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) > +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) > +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) > +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) > +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) > +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) > +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) > +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) > > /* Flags defined for counter start function */ > -#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) > +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) > > /* Flags defined for counter stop function */ > -#define SBI_PMU_STOP_FLAG_RESET (1 << 0) > +#define SBI_PMU_STOP_FLAG_RESET BIT(0) > > enum sbi_ext_dbcn_fid { > SBI_EXT_DBCN_CONSOLE_WRITE = 0, > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index babf1b9a4dbe..a83ae82301e3 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -386,7 +386,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) > cmask = 1; > } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) { > cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; > - cmask = 1UL << (CSR_INSTRET - CSR_CYCLE); > + cmask = BIT(CSR_INSTRET - CSR_CYCLE); > } > } > > -- > 2.34.1 > Other than the commit message, Reviewed-by: Andrew Jones Thanks, drew From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25AABCD1284 for ; Thu, 4 Apr 2024 11:08:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id xh12-20020a170906da8c00b00a4e579ce949sm6017903ejb.51.2024.04.04.04.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Apr 2024 04:08:12 -0700 (PDT) Date: Thu, 4 Apr 2024 13:08:11 +0200 From: Andrew Jones To: Atish Patra Cc: linux-kernel@vger.kernel.org, Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: Re: [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Message-ID: <20240404-9a84f2090d00f6b994e1de7c@orel> References: <20240403080452.1007601-1-atishp@rivosinc.com> <20240403080452.1007601-5-atishp@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240403080452.1007601-5-atishp@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240404_040816_103554_C539A308 X-CRM114-Status: GOOD ( 18.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Apr 03, 2024 at 01:04:33AM -0700, Atish Patra wrote: > It is a good practice to use BIT() instead of (1UL << x). (1UL << x) isn't generally a problem. The problem is with (1 << x). > Replace the current usages with BIT(). > > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/sbi.h | 20 ++++++++++---------- > drivers/perf/riscv_pmu_sbi.c | 2 +- > 2 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index ef8311dafb91..4afa2cd01bae 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -233,20 +233,20 @@ enum sbi_pmu_ctr_type { > #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF > > /* Flags defined for config matching function */ > -#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) > -#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) > -#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) > -#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) > -#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) > -#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) > -#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) > -#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) > +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) > +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) > +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) > +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) > +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) > +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) > +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) > +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) > > /* Flags defined for counter start function */ > -#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) > +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) > > /* Flags defined for counter stop function */ > -#define SBI_PMU_STOP_FLAG_RESET (1 << 0) > +#define SBI_PMU_STOP_FLAG_RESET BIT(0) > > enum sbi_ext_dbcn_fid { > SBI_EXT_DBCN_CONSOLE_WRITE = 0, > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index babf1b9a4dbe..a83ae82301e3 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -386,7 +386,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) > cmask = 1; > } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) { > cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; > - cmask = 1UL << (CSR_INSTRET - CSR_CYCLE); > + cmask = BIT(CSR_INSTRET - CSR_CYCLE); > } > } > > -- > 2.34.1 > Other than the commit message, Reviewed-by: Andrew Jones Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv