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Wed, 17 Apr 2024 21:55:11 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43HLsggm015445 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Apr 2024 21:54:42 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Apr 2024 14:54:41 -0700 Date: Wed, 17 Apr 2024 14:54:41 -0700 From: Elliot Berman To: Sudeep Holla CC: Bjorn Andersson , Konrad Dybcio , Sebastian Reichel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , , Subject: Re: [PATCH v2 0/4] Implement vendor resets for PSCI SYSTEM_RESET2 Message-ID: <20240417140957985-0700.eberman@hu-eberman-lv.qualcomm.com> References: <20240414-arm-psci-system_reset2-vendor-reboots-v2-0-da9a055a648f@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Fj2qyuwf4HChIqXQIWRk-MgKV3h44KJW X-Proofpoint-GUID: Fj2qyuwf4HChIqXQIWRk-MgKV3h44KJW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-17_18,2024-04-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=846 clxscore=1011 mlxscore=0 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404170156 On Tue, Apr 16, 2024 at 10:35:22AM +0100, Sudeep Holla wrote: > On Sun, Apr 14, 2024 at 12:30:23PM -0700, Elliot Berman wrote: > > The PSCI SYSTEM_RESET2 call allows vendor firmware to define additional > > reset types which could be mapped to the reboot argument. > > > > Setting up reboot on Qualcomm devices can be inconsistent from chipset > > to chipset. > > That doesn't sound good. Do you mean PSCI SYSTEM_RESET doesn't work as > expected ? Does it mean it is not conformant to the specification ? > I was motivating the reason for using SYSTEM_RESET2. How to set the PMIC register and IMEM cookie can change between chipsets. Using SYSTEM_RESET2 alows us to abstract how to perform the reset. > > Generally, there is a PMIC register that gets written to > > decide the reboot type. There is also sometimes a cookie that can be > > written to indicate that the bootloader should behave differently than a > > regular boot. These knobs evolve over product generations and require > > more drivers. Qualcomm firmwares are beginning to expose vendor > > SYSTEM_RESET2 types to simplify driver requirements from Linux. > > > > Why can't this be fully userspace driven ? What is the need to keep the > cookie in the DT ? As Dmitry pointed out, this information isn't discoverable. I suppose we could technically use bootconfig or kernel command-line to convey the map although I think devicetree is the right spot for this mapping. - Other vendor-specific bits for PSCI are described in the devicetree. One example is the suspend param (e.g. the StateID) for cpu idle states. - Describing firmware bits in the DT isn't unprecedented, and putting this information outside the DT means that other OSes (besides Linux) need their own way to convey this information. - PSCI would be the odd one out that reboot mode map is not described in DT. Other reboot-mode drivers specify the mapping in the DT. Userspace that runs with firmware that support vendor reset2 need to make sure they can configure the mapping early enough. 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Wed, 17 Apr 2024 21:55:11 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43HLsggm015445 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Apr 2024 21:54:42 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Apr 2024 14:54:41 -0700 Date: Wed, 17 Apr 2024 14:54:41 -0700 From: Elliot Berman To: Sudeep Holla CC: Bjorn Andersson , Konrad Dybcio , Sebastian Reichel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , , Subject: Re: [PATCH v2 0/4] Implement vendor resets for PSCI SYSTEM_RESET2 Message-ID: <20240417140957985-0700.eberman@hu-eberman-lv.qualcomm.com> References: <20240414-arm-psci-system_reset2-vendor-reboots-v2-0-da9a055a648f@quicinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Fj2qyuwf4HChIqXQIWRk-MgKV3h44KJW X-Proofpoint-GUID: Fj2qyuwf4HChIqXQIWRk-MgKV3h44KJW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-17_18,2024-04-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=846 clxscore=1011 mlxscore=0 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404170156 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240417_145521_145174_F886DE0E X-CRM114-Status: GOOD ( 24.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 16, 2024 at 10:35:22AM +0100, Sudeep Holla wrote: > On Sun, Apr 14, 2024 at 12:30:23PM -0700, Elliot Berman wrote: > > The PSCI SYSTEM_RESET2 call allows vendor firmware to define additional > > reset types which could be mapped to the reboot argument. > > > > Setting up reboot on Qualcomm devices can be inconsistent from chipset > > to chipset. > > That doesn't sound good. Do you mean PSCI SYSTEM_RESET doesn't work as > expected ? Does it mean it is not conformant to the specification ? > I was motivating the reason for using SYSTEM_RESET2. How to set the PMIC register and IMEM cookie can change between chipsets. Using SYSTEM_RESET2 alows us to abstract how to perform the reset. > > Generally, there is a PMIC register that gets written to > > decide the reboot type. There is also sometimes a cookie that can be > > written to indicate that the bootloader should behave differently than a > > regular boot. These knobs evolve over product generations and require > > more drivers. Qualcomm firmwares are beginning to expose vendor > > SYSTEM_RESET2 types to simplify driver requirements from Linux. > > > > Why can't this be fully userspace driven ? What is the need to keep the > cookie in the DT ? As Dmitry pointed out, this information isn't discoverable. I suppose we could technically use bootconfig or kernel command-line to convey the map although I think devicetree is the right spot for this mapping. - Other vendor-specific bits for PSCI are described in the devicetree. One example is the suspend param (e.g. the StateID) for cpu idle states. - Describing firmware bits in the DT isn't unprecedented, and putting this information outside the DT means that other OSes (besides Linux) need their own way to convey this information. - PSCI would be the odd one out that reboot mode map is not described in DT. Other reboot-mode drivers specify the mapping in the DT. Userspace that runs with firmware that support vendor reset2 need to make sure they can configure the mapping early enough. Thanks, Elliot _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel