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Fri, 19 Apr 2024 10:50:16 -0700 (PDT) Date: Fri, 19 Apr 2024 19:50:13 +0200 Mime-Version: 1.0 X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog Message-ID: <20240419175013.3983824-1-ardb+git@google.com> Subject: [PATCH] ArmVirtPkg/ArmVirtQemu: always build XIP code with strict alignment From: Ard Biesheuvel To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, Ard Biesheuvel , Jonathan Cameron , Richard Henderson , "=?UTF-8?q?Philippe=20Mathieu-Daud=E9?=" , Idan Horowitz , qemu-arm@nongnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::114a; envelope-from=32K4iZggKCPcZqca+fhsfnnfkd.bnlpdlt-Zqlmnmfmt.nqf@flex--ardb.bounces.google.com; helo=mail-yw1-x114a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: E3ZQEFmTpltm From: Ard Biesheuvel The optimization that enabled entry with MMU and caches enabled at EL1 removed the strict alignment requirement for XIP code (roughly, any code that might execute with the MMU and caches off, which means SEC and PEI phase modules but also *all* BASE libraries), on the basis that QEMU can only run guest payloads at EL2 in TCG emulation, which used to ignore alignment violations, and execution at EL1 would always occur with the MMU enabled. This assumption no longer holds: not only does QEMU now enforce strict alignment for memory accesses with device semantics, there are also cases where this code might execute at EL2 under virtualization (i.e., under NV2 nested virtualization) where the strict alignment is required too. The latter case could be optimized too, by enabling VHE and pretending execution is occurring at EL1, which would allow the existing logic for entry with the MMU enabled to be reused. However, this would leave non-VHE CPUs behind. So in summary, strict alignment needs to be enforced for any code that may execute with the MMU off, so drop the override that sets the XIP flags to the empty string. Cc: Jonathan Cameron Cc: Richard Henderson Cc: Philippe Mathieu-Daud=EF=BF=BD Cc: Idan Horowitz Cc: qemu-arm@nongnu.org Signed-off-by: Ard Biesheuvel --- ArmVirtPkg/ArmVirtQemu.dsc | 2 -- 1 file changed, 2 deletions(-) diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index e48c75b5e99f..f6f78359552d 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -124,8 +124,6 @@ [LibraryClasses.common.UEFI_DRIVER] [BuildOptions] !if $(CAVIUM_ERRATUM_27456) =3D=3D TRUE GCC:*_*_AARCH64_PP_FLAGS =3D -DCAVIUM_ERRATUM_27456 -!else - GCC:*_*_AARCH64_CC_XIPFLAGS =3D=3D !endif =20 !include NetworkPkg/NetworkBuildOptions.dsc.inc -- 2.44.0.769.g3c40516874-goog