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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1713778055; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=Co44Q9mlr4zNsi4wNMbg2xr+Hkh3wz3o/Kg+Jwyh0d4=; b=jCfpUiFTGUPXPYsp3pm3Ur6ev6kvmfoiYjjLuoCshXsFTzZ3APSPHDYHcs1KGuvM5BL0iW 7aAzgJsJ9ebxp9++NZG/L5IrT4RJefIR2W2pZ6UopAdmIvUcqyP7ak3IYCYAWHTf1G0ATZ 7vOqqujywPWxxJsaA+Zm3RxdJ7Srduk= From: Zenghui Yu To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: agraf@csgraf.de, peter.maydell@linaro.org, wanghaibin.wang@huawei.com, Zenghui Yu Subject: [PATCH] hvf: arm: Remove PL1_WRITE_MASK Date: Mon, 22 Apr 2024 17:27:15 +0800 Message-Id: <20240422092715.71973-1-zenghui.yu@linux.dev> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT Received-SPF: pass client-ip=2001:41d0:203:375::bc; envelope-from=zenghui.yu@linux.dev; helo=out-188.mta1.migadu.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 22 Apr 2024 10:51:07 -0400 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: YTqcQug3Vfqg As it had never been used since the first commit a1477da3ddeb ("hvf: Add Apple Silicon support"). Signed-off-by: Zenghui Yu --- target/arm/hvf/hvf.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 65a5601804..015e96a6d3 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -150,7 +150,6 @@ void hvf_arm_init_debug(void) #define HVF_SYSREG(crn, crm, op0, op1, op2) \ ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) -#define PL1_WRITE_MASK 0x4 #define SYSREG_OP0_SHIFT 20 #define SYSREG_OP0_MASK 0x3 -- 2.34.1