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X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.202.227.76] X-ClientProxiedBy: lhrpeml500006.china.huawei.com (7.191.161.198) To lhrpeml500005.china.huawei.com (7.191.163.240) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: 5lUUG5jqgVgr On Fri, 19 Apr 2024 19:50:13 +0200 Ard Biesheuvel wrote: > From: Ard Biesheuvel >=20 > The optimization that enabled entry with MMU and caches enabled at EL1 > removed the strict alignment requirement for XIP code (roughly, any code > that might execute with the MMU and caches off, which means SEC and PEI > phase modules but also *all* BASE libraries), on the basis that QEMU can > only run guest payloads at EL2 in TCG emulation, which used to ignore > alignment violations, and execution at EL1 would always occur with the > MMU enabled. >=20 > This assumption no longer holds: not only does QEMU now enforce strict > alignment for memory accesses with device semantics, there are also > cases where this code might execute at EL2 under virtualization (i.e., > under NV2 nested virtualization) where the strict alignment is required > too. >=20 > The latter case could be optimized too, by enabling VHE and pretending > execution is occurring at EL1, which would allow the existing logic for > entry with the MMU enabled to be reused. However, this would leave > non-VHE CPUs behind. >=20 > So in summary, strict alignment needs to be enforced for any code that > may execute with the MMU off, so drop the override that sets the XIP > flags to the empty string. >=20 > Cc: Jonathan Cameron > Cc: Richard Henderson > Cc: Philippe Mathieu-Daud=EF=BF=BD > Cc: Idan Horowitz > Cc: qemu-arm@nongnu.org > Signed-off-by: Ard Biesheuvel This matches what I was testing with locally. Thanks sorting this out. Tested-by: Jonathan Cameron Reviewed-by: Jonathan Cameron > --- > ArmVirtPkg/ArmVirtQemu.dsc | 2 -- > 1 file changed, 2 deletions(-) >=20 > diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc > index e48c75b5e99f..f6f78359552d 100644 > --- a/ArmVirtPkg/ArmVirtQemu.dsc > +++ b/ArmVirtPkg/ArmVirtQemu.dsc > @@ -124,8 +124,6 @@ [LibraryClasses.common.UEFI_DRIVER] > [BuildOptions] >=20 > !if $(CAVIUM_ERRATUM_27456) =3D=3D TRUE >=20 > GCC:*_*_AARCH64_PP_FLAGS =3D -DCAVIUM_ERRATUM_27456 >=20 > -!else >=20 > - GCC:*_*_AARCH64_CC_XIPFLAGS =3D=3D >=20 > !endif >=20 > =20 >=20 > !include NetworkPkg/NetworkBuildOptions.dsc.inc >=20 > -- > 2.44.0.769.g3c40516874-goog >=20