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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(376005)(82310400014)(36860700004)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2024 08:42:09.9056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e704d457-1b8d-40db-27cd-08dc643a6e3d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6787 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Rodrigo Siqueira Add dcn301_fpu prefix to some of the FPU function with the required adjustments. Acked-by: Wayne Lin Signed-off-by: Rodrigo Siqueira --- .../amd/display/dc/dml/dcn301/dcn301_fpu.c | 4 ++-- .../amd/display/dc/dml/dcn301/dcn301_fpu.h | 7 +++---- .../dc/resource/dcn301/dcn301_resource.c | 19 +++++++++++++------ 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c index 6ce90678b33c..0c0b2d67c9cd 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c @@ -320,7 +320,7 @@ static void calculate_wm_set_for_vlevel(int vlevel, } -void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) { struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool); @@ -409,7 +409,7 @@ void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info) dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; } -void dcn301_calculate_wm_and_dlg_fp(struct dc *dc, +void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h index 774b0fdfc80b..3e103e23dc6f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h @@ -26,15 +26,14 @@ #ifndef __DCN301_FPU_H__ #define __DCN301_FPU_H__ -void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); +void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info); +void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); void dcn301_fpu_set_wm_ranges(int i, struct pp_smu_wm_range_sets *ranges, struct _vcs_dpi_soc_bounding_box_st *loaded_bb); -void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info); - -void dcn301_calculate_wm_and_dlg_fp(struct dc *dc, +void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 7538b548c572..346cec70de96 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1363,14 +1363,21 @@ static void set_wm_ranges( pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); } -static void dcn301_calculate_wm_and_dlg( - struct dc *dc, struct dc_state *context, - display_e2e_pipe_params_st *pipes, - int pipe_cnt, - int vlevel) +static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) { DC_FP_START(); - dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); + dcn301_fpu_update_bw_bounding_box(dc, bw_params); + DC_FP_END(); +} + +static void dcn301_calculate_wm_and_dlg(struct dc *dc, + struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int pipe_cnt, + int vlevel_req) +{ + DC_FP_START(); + dcn301_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel_req); DC_FP_END(); } -- 2.37.3