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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(36860700004)(82310400014)(376005)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2024 08:53:07.1017 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f6c03fb-44a1-4d37-dd07-08dc643bf5fe X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4415 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alvin Lee [Description] Today for MED update type we do not call update clocks. However, for FPO the assumption is that update clocks should be called to disable P-State switch before any HW programming since FPO in FW and driver are not synchronized. This causes an issue where on a MED update, an FPO P-State switch could be taking place, then driver forces P-State disallow in the below code and prevents FPO from completing the sequence. In this case we add a check to avoid re-programming (and thus re-setting) the P-State force register by only reprogramming if the pipe was not previously Subvp or FPO. The assumption is that the P-State force register should be programmed correctly the first time SubVP / FPO was enabled, so there's no need to update / reset it if the pipe config has never exited SubVP / FPO. Reviewed-by: Samson Tam Acked-by: Wayne Lin Signed-off-by: Alvin Lee --- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 9f1a86ddadb5..272c4cdfbfe3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -614,10 +614,26 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context) */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; struct hubp *hubp = pipe->plane_res.hubp; + /* Today for MED update type we do not call update clocks. However, for FPO + * the assumption is that update clocks should be called to disable P-State + * switch before any HW programming since FPO in FW and driver are not + * synchronized. This causes an issue where on a MED update, an FPO P-State + * switch could be taking place, then driver forces P-State disallow in the below + * code and prevents FPO from completing the sequence. In this case we add a check + * to avoid re-programming (and thus re-setting) the P-State force register by + * only reprogramming if the pipe was not previously Subvp or FPO. The assumption + * is that the P-State force register should be programmed correctly the first + * time SubVP / FPO was enabled, so there's no need to update / reset it if the + * pipe config has never exited SubVP / FPO. + */ if (pipe->stream && (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN || - pipe->stream->fpo_in_use)) { + pipe->stream->fpo_in_use) && + (!old_pipe->stream || + (dc_state_get_pipe_subvp_type(context, old_pipe) != SUBVP_MAIN && + !old_pipe->stream->fpo_in_use))) { if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) -- 2.37.3