diff for duplicates of <20240426100820.14762-11-ajones@ventanamicro.com> diff --git a/a/1.txt b/N1/1.txt index 7536d88..f4aa6da 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,4 +1,4 @@ -From: Christoph M?llner <christoph.muellner@vrull.eu> +From: Christoph Müllner <christoph.muellner@vrull.eu> RISC-V code uses the generic ticket lock implementation, which calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire(). @@ -16,7 +16,7 @@ approach Andrea Parri also suggested. The Zawrs specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc -Signed-off-by: Christoph M?llner <christoph.muellner@vrull.eu> +Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Co-developed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- @@ -235,3 +235,9 @@ index 3ed2359eae35..02de9eaa3f42 100644 __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), -- 2.44.0 + + +_______________________________________________ +linux-riscv mailing list +linux-riscv@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-riscv diff --git a/a/content_digest b/N1/content_digest index 994805d..0769bb8 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,10 +2,27 @@ "From\0Andrew Jones <ajones@ventanamicro.com>\0" "Subject\0[PATCH v3 3/6] riscv: Add Zawrs support for spinlocks\0" "Date\0Fri, 26 Apr 2024 12:08:23 +0200\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0linux-riscv@lists.infradead.org" + kvm-riscv@lists.infradead.org + " devicetree@vger.kernel.org\0" + "Cc\0paul.walmsley@sifive.com" + palmer@dabbelt.com + aou@eecs.berkeley.edu + conor.dooley@microchip.com + anup@brainfault.org + atishp@atishpatra.org + robh@kernel.org + krzysztof.kozlowski+dt@linaro.org + conor+dt@kernel.org + christoph.muellner@vrull.eu + heiko@sntech.de + charlie@rivosinc.com + David.Laight@aculab.com + parri.andrea@gmail.com + " luxu.kernel@bytedance.com\0" "\00:1\0" "b\0" - "From: Christoph M?llner <christoph.muellner@vrull.eu>\n" + "From: Christoph M\303\274llner <christoph.muellner@vrull.eu>\n" "\n" "RISC-V code uses the generic ticket lock implementation, which calls\n" "the macros smp_cond_load_relaxed() and smp_cond_load_acquire().\n" @@ -23,7 +40,7 @@ "The Zawrs specification can be found here:\n" "https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc\n" "\n" - "Signed-off-by: Christoph M?llner <christoph.muellner@vrull.eu>\n" + "Signed-off-by: Christoph M\303\274llner <christoph.muellner@vrull.eu>\n" "Co-developed-by: Andrew Jones <ajones@ventanamicro.com>\n" "Signed-off-by: Andrew Jones <ajones@ventanamicro.com>\n" "---\n" @@ -241,6 +258,12 @@ " \t__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),\n" " \t__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),\n" "-- \n" - 2.44.0 + "2.44.0\n" + "\n" + "\n" + "_______________________________________________\n" + "linux-riscv mailing list\n" + "linux-riscv@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-riscv -01aec16c99b88f867d802cae8d1750c11457a0b2245c8af03493c3d5cf301e3c +0bcb67b1cc405b1a229690a7dbccf62d743bf9c2330850ae43558440da09a5e9
diff --git a/a/1.txt b/N2/1.txt index 7536d88..5fd7ee6 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,4 +1,4 @@ -From: Christoph M?llner <christoph.muellner@vrull.eu> +From: Christoph Müllner <christoph.muellner@vrull.eu> RISC-V code uses the generic ticket lock implementation, which calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire(). @@ -16,7 +16,7 @@ approach Andrea Parri also suggested. The Zawrs specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc -Signed-off-by: Christoph M?llner <christoph.muellner@vrull.eu> +Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Co-developed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- diff --git a/a/content_digest b/N2/content_digest index 994805d..92520ce 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,10 +2,27 @@ "From\0Andrew Jones <ajones@ventanamicro.com>\0" "Subject\0[PATCH v3 3/6] riscv: Add Zawrs support for spinlocks\0" "Date\0Fri, 26 Apr 2024 12:08:23 +0200\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0linux-riscv@lists.infradead.org" + kvm-riscv@lists.infradead.org + " devicetree@vger.kernel.org\0" + "Cc\0paul.walmsley@sifive.com" + palmer@dabbelt.com + aou@eecs.berkeley.edu + conor.dooley@microchip.com + anup@brainfault.org + atishp@atishpatra.org + robh@kernel.org + krzysztof.kozlowski+dt@linaro.org + conor+dt@kernel.org + christoph.muellner@vrull.eu + heiko@sntech.de + charlie@rivosinc.com + David.Laight@aculab.com + parri.andrea@gmail.com + " luxu.kernel@bytedance.com\0" "\00:1\0" "b\0" - "From: Christoph M?llner <christoph.muellner@vrull.eu>\n" + "From: Christoph M\303\274llner <christoph.muellner@vrull.eu>\n" "\n" "RISC-V code uses the generic ticket lock implementation, which calls\n" "the macros smp_cond_load_relaxed() and smp_cond_load_acquire().\n" @@ -23,7 +40,7 @@ "The Zawrs specification can be found here:\n" "https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc\n" "\n" - "Signed-off-by: Christoph M?llner <christoph.muellner@vrull.eu>\n" + "Signed-off-by: Christoph M\303\274llner <christoph.muellner@vrull.eu>\n" "Co-developed-by: Andrew Jones <ajones@ventanamicro.com>\n" "Signed-off-by: Andrew Jones <ajones@ventanamicro.com>\n" "---\n" @@ -243,4 +260,4 @@ "-- \n" 2.44.0 -01aec16c99b88f867d802cae8d1750c11457a0b2245c8af03493c3d5cf301e3c +576665f7b4e6447c85f08092547321213acf518037ecb483e5c85da196a9ca69
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