From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53CE34654B for ; Sat, 27 Apr 2024 09:54:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.43 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714211698; cv=none; b=D9Nmd45ZHyQWSslFmRvu06RDSTZ1jr2a9JHJiiXa1J7zDuSx5Ci7T9/wQEsIAmQCaxFsDasBEtDL3KglPmBzhnAKLn1RdSBsNtd3S7hO2/nUC5O06hFhyQc1VSggVkeePdZVymUKthEj3dJKihwyoCF36nWQg4qr0ZUaluezmdU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714211698; c=relaxed/simple; bh=oAKyMTR8eWOSyqxbhlem5MYmleLa9lzfZXEEcetSXnM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=KNbZYVEhjxOkl+SK2V59tByQw/2qgTZk8o7cfDTWTU8tEbipXlN5N+BTRglpIZyA8gPEpf/4fp52HzK4iGqGZV2pZT8xIy8szvuDQH/Q4NmRgJ0qbkRmf2Aj9tmB5q91rDj8dMr7kNuMsTCnOdrxNr/UlZ8Ia9MGyDkESYJwtSo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=rjbUlxk2; arc=none smtp.client-ip=209.85.216.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rjbUlxk2" Received: by mail-pj1-f43.google.com with SMTP id 98e67ed59e1d1-2b07f6b38daso905893a91.1 for ; Sat, 27 Apr 2024 02:54:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714211695; x=1714816495; darn=vger.kernel.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=q7IJCY5rJWmDi7bRkGY/6TU0zJug2sXYMpCIYdgYukw=; b=rjbUlxk2e7bHQLJkTEDScQs9ZP23EPeVPFtV6zJYKHO+0S1B8pN7ld9U0JlukRfyXM NcxfANbIhJFq8zWB6TY2nWiwr783kv8jaX0FQdqdYxm9cdfWOvoMx0f0IwMrjOscwslH aXoOBLYpzdWvSR3UDtr113Ddz3PIoXkzYcigG7EgSS6TYBUJlePY9Wi8qK+eEYCerEWl xsMz4EIVXjyiG5E0ABWqsENmGuu3AdYnnTjiZdjp30IImNMYxk3fdsBHvg38xN9EdIYS bj/XMI4/ZpQEKdaqegeZT+6TlOVt7UxQU1+TSHGkthR6gyL8LFJpy+5nJWGa8mDbISUr L7Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714211695; x=1714816495; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=q7IJCY5rJWmDi7bRkGY/6TU0zJug2sXYMpCIYdgYukw=; b=a2JiSgNJaTZtlKg9CmAfdyBLiZaSFEGQcyDs5PpnypLpM4eLpUQBOdm0MR/bSudfIw ntqsmk/HSAxTuXG0CST8llTV6VGHAailAKL0vkJUidqtobVhIjLH1iyxSDVslSwp4Pqa UELCrmF1I/YGr8bpXTUOm4SBCHI7trEhMLMoNIKIL7qRa2INJQE/hVRee6zbdGbpoP2p ru1R6gTKncti6OAw4j73Hjq4t26WbKhC73BeMwN7br/j3i2FTJ2EQxrwk4x7ZoB3AigQ L2xRoPoAbdkYicCtxiQS7c0mJJwAWakXfsW5TMvLo75xXIqX2eO5H5RoP6y4LR54oTW4 NNjA== X-Forwarded-Encrypted: i=1; AJvYcCXf05PIWGGl6hAfb/qJWUvh14QVmeSnCq/9MKwMfN4KpOcoHuWHXAYq+8F2Nv4RtAAnXw+8verRqkRnCThj3t4HWz6i X-Gm-Message-State: AOJu0Ywy+EzBYgZ49pmrN2kX3aCybR4KLm7cAbH8aPg9I7Dge6UalpTW AN8YOX24z2zBl6KahaMxNp8hlC/D+9lIk55F4MgRdMXJ+tWW3T4xoDwFpMjYlA== X-Google-Smtp-Source: AGHT+IHbaVLmro9zr9PHmAJzQU4EgUaA+TXAd31urwcQTwZNnANEbssC6ijmrdtMi2g14n+SXgcytg== X-Received: by 2002:a17:90b:246:b0:2aa:cadb:d290 with SMTP id fz6-20020a17090b024600b002aacadbd290mr7383922pjb.13.1714211694536; Sat, 27 Apr 2024 02:54:54 -0700 (PDT) Received: from thinkpad ([117.213.97.210]) by smtp.gmail.com with ESMTPSA id y10-20020a17090ad70a00b002a63e966fd7sm15753781pju.47.2024.04.27.02.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Apr 2024 02:54:54 -0700 (PDT) Date: Sat, 27 Apr 2024 15:24:44 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 06/11] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback Message-ID: <20240427095444.GK1981@thinkpad> References: <20240402-pci2_upstream-v3-0-803414bdb430@nxp.com> <20240402-pci2_upstream-v3-6-803414bdb430@nxp.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240402-pci2_upstream-v3-6-803414bdb430@nxp.com> On Tue, Apr 02, 2024 at 10:33:42AM -0400, Frank Li wrote: PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK > Instead of using the switch case statement to enable/disable the reference > clock handled by this driver itself, let's introduce a new callback > set_ref_clk() and define it for platforms that require it. This simplifies > the code. > > Signed-off-by: Frank Li > --- > drivers/pci/controller/dwc/pcie-imx.c | 119 ++++++++++++++++------------------ > 1 file changed, 55 insertions(+), 64 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c > index e93070d60df52..77dae5c3f7057 100644 > --- a/drivers/pci/controller/dwc/pcie-imx.c > +++ b/drivers/pci/controller/dwc/pcie-imx.c > @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { > const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; > const struct pci_epc_features *epc_features; > int (*init_phy)(struct imx_pcie *pcie); > + int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); > }; > > struct imx_pcie { > @@ -585,77 +586,54 @@ static int imx_pcie_attach_pd(struct device *dev) > return 0; > } > > -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) > +static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > { > - unsigned int offset; > - int ret = 0; > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, > + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); > > - switch (imx_pcie->drvdata->variant) { > - case IMX6SX: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); > - break; > - case IMX6QP: > - case IMX6Q: > + return 0; > +} > + > +static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > +{ > + if (enable) { > /* power up core phy and enable ref clock */ > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0); > /* > - * the async reset input need ref clock to sync internally, > - * when the ref clock comes after reset, internal synced > - * reset time is too short, cannot meet the requirement. > - * add one ~10us delay here. > + * the async reset input need ref clock to sync internally, when the ref clock comes > + * after reset, internal synced reset time is too short, cannot meet the > + * requirement.add one ~10us delay here. Please wrap the comments to 80 column width. > */ > usleep_range(10, 100); > regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); > - break; > - case IMX7D: > - case IMX95: > - case IMX95_EP: > - break; > - case IMX8MM: > - case IMX8MM_EP: > - case IMX8MQ: > - case IMX8MQ_EP: > - case IMX8MP: > - case IMX8MP_EP: > - offset = imx_pcie_grp_offset(imx_pcie); > - /* > - * Set the over ride low and enabled > - * make sure that REF_CLK is turned on. > - */ > - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, > - 0); > - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); > - break; > + IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN); > + } else { > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); > } > > - return ret; > + return 0; > } > > -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) > +static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > { > - switch (imx_pcie->drvdata->variant) { > - case IMX6QP: > - case IMX6Q: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_TEST_PD, > - IMX6Q_GPR1_PCIE_TEST_PD); > - break; > - case IMX7D: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, > - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, > - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); > - break; > - default: > - break; > - } > + int offset = imx_pcie_grp_offset(imx_pcie); > + > + /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/ > + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, > + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); > + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, > + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); Extra space after : > + return 0; > +} > + > +static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > +{ > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, > + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); > + return 0; > } > > static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) > @@ -668,10 +646,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) > if (ret) > return ret; > > - ret = imx_pcie_enable_ref_clk(imx_pcie); > - if (ret) { > - dev_err(dev, "unable to enable pcie ref clock\n"); > - goto err_ref_clk; > + if (imx_pcie->drvdata->set_ref_clk) { > + ret = imx_pcie->drvdata->set_ref_clk(imx_pcie, true); > + if (ret) { > + dev_err(dev, "unable to enable pcie ref clock\n"); 'Failed to enable PCIe REFCLK' - Mani -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2D58C4345F for ; Sat, 27 Apr 2024 09:55:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1vPD6RSSK7a+/TPgSM2sBclp99l9f4V+FOz3nhSXNG4=; b=kbviVapWNh6v2B hpBe0AIMwPEubgVwNnX4JkWUk0loorRnQ0jTS8FB5B2ZRK4n3RjREoJ8Xg/1zssOxsyLCwI9Lfzfd 7A0xS+M9Eb/vbo2OHryuXyuazTh6P4gzgEUy5CtFd8kzsKDvp092eWJ9fPpXJd1zwk2KadAKm4SIZ SyAhO7CgFkH0GtGf/xCQu5cNRxyp5IIAQn9iNXbqF9oinYWujIuNCyHUI/PK7d0fXYaQGI2XxsDu1 44MfzKLt5Jw+AYDsda0WBkXufnsDtpu3fSFbo+mk8exk5CNY1mR+Dv5qWVC5Q/YcR2+Nx5gwinzbu sbu0jYPljsdhFcrOMbtA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s0elo-0000000FGOH-0oYb; Sat, 27 Apr 2024 09:55:00 +0000 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s0ell-0000000FGNW-0Bll for linux-arm-kernel@lists.infradead.org; Sat, 27 Apr 2024 09:54:59 +0000 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6ed2170d89fso2750520b3a.1 for ; Sat, 27 Apr 2024 02:54:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714211694; x=1714816494; darn=lists.infradead.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=q7IJCY5rJWmDi7bRkGY/6TU0zJug2sXYMpCIYdgYukw=; b=rL5izviwZzh5tzIYim0rVbn4WtNLsS3yCRq/l/JAXRgBEbiwSJpcAMJZEpQJyNeiu6 uFKnlJN1gBsOG5sFkQRxt/k4cU31nYfwpvjmVfitSYVLP2jsq+0qrd/uw5eICIl3LMSp gL/AcsO4ttfiAaZIWYaFAKbGj60/GBmSEIZ7ZcGXP0YPmgJUbjZa7JM8FJp/HgsmMteW r9zI4zn+KI1NuyOB9ShH9xfUu0XDufEZ8gG2Vae/atWQ4KgI4ps6S31yvSvNx66r23L0 kill4OriSZju2beMUk/p3hm55ErZhzvjwd7wVNKxsbcsoYFubIOY1p5TKpVrLDc6k1nz LUsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714211694; x=1714816494; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=q7IJCY5rJWmDi7bRkGY/6TU0zJug2sXYMpCIYdgYukw=; b=C8W30FP+Lb4s2+Vm8/1jPK45H971LswzFqoDznOg7ytInom4xZOs0Cw9HXgM4w3asE unzTOspVBZS/hVy6SdhzitATX4Dr2e02BD50eelD+AgbyL7cOgwBCcae9bV50rPD1NKO 6OT0JiUnSAQtXanxdK80gm+PkT/uz7wsBihpH/ZTRmUd7bM9j2O5Up14U2AwAwQ+VnGo KmgtMlP5f8ZwxtK7l42fsmbPmkSIVZm4hZ5QiemMHmPXQZkI3ZyScwAgj0pTqpCSNi9v iYURMHkTK+DfEb2o9X2e6+asu/I50ToOX4A9QmcX6/H1KTwVP2ACNZWR6QWxuT/TYZvG /BfQ== X-Forwarded-Encrypted: i=1; AJvYcCVTIL3FbqCU6Wzj14pW80Tqf3yq0gzFb2nqDmFUDVmmc7N7n3YRDnrf9FVwU+zrwgUM5bhXlOTRH6ZBwOr3riIQlbBemWUm/jL8++qp+tYbDOhBm4s= X-Gm-Message-State: AOJu0YxffD3EwN+iWdJRbfB0J0poQO8iiuONm+gooMMD2W99B5HG/np0 dMkAYdWIbvLI1yz6/D0fRY5tjqtE4qmiRKc3UtsiW27Ts8USSoY4ZBROby0KkQ== X-Google-Smtp-Source: AGHT+IHbaVLmro9zr9PHmAJzQU4EgUaA+TXAd31urwcQTwZNnANEbssC6ijmrdtMi2g14n+SXgcytg== X-Received: by 2002:a17:90b:246:b0:2aa:cadb:d290 with SMTP id fz6-20020a17090b024600b002aacadbd290mr7383922pjb.13.1714211694536; Sat, 27 Apr 2024 02:54:54 -0700 (PDT) Received: from thinkpad ([117.213.97.210]) by smtp.gmail.com with ESMTPSA id y10-20020a17090ad70a00b002a63e966fd7sm15753781pju.47.2024.04.27.02.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Apr 2024 02:54:54 -0700 (PDT) Date: Sat, 27 Apr 2024 15:24:44 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 06/11] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback Message-ID: <20240427095444.GK1981@thinkpad> References: <20240402-pci2_upstream-v3-0-803414bdb430@nxp.com> <20240402-pci2_upstream-v3-6-803414bdb430@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240402-pci2_upstream-v3-6-803414bdb430@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240427_025457_146406_CE9AAB72 X-CRM114-Status: GOOD ( 26.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVHVlLCBBcHIgMDIsIDIwMjQgYXQgMTA6MzM6NDJBTSAtMDQwMCwgRnJhbmsgTGkgd3JvdGU6 CgpQQ0k6IGlteDY6IEludHJvZHVjZSBTb0Mgc3BlY2lmaWMgY2FsbGJhY2tzIGZvciBjb250cm9s bGluZyBSRUZDTEsKCj4gSW5zdGVhZCBvZiB1c2luZyB0aGUgc3dpdGNoIGNhc2Ugc3RhdGVtZW50 IHRvIGVuYWJsZS9kaXNhYmxlIHRoZSByZWZlcmVuY2UKPiBjbG9jayBoYW5kbGVkIGJ5IHRoaXMg ZHJpdmVyIGl0c2VsZiwgbGV0J3MgaW50cm9kdWNlIGEgbmV3IGNhbGxiYWNrCj4gc2V0X3JlZl9j bGsoKSBhbmQgZGVmaW5lIGl0IGZvciBwbGF0Zm9ybXMgdGhhdCByZXF1aXJlIGl0LiBUaGlzIHNp bXBsaWZpZXMKPiB0aGUgY29kZS4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBGcmFuayBMaSA8RnJhbmsu TGlAbnhwLmNvbT4KPiAtLS0KPiAgZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1pbXgu YyB8IDExOSArKysrKysrKysrKysrKysrLS0tLS0tLS0tLS0tLS0tLS0tCj4gIDEgZmlsZSBjaGFu Z2VkLCA1NSBpbnNlcnRpb25zKCspLCA2NCBkZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEv ZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1pbXguYyBiL2RyaXZlcnMvcGNpL2NvbnRy b2xsZXIvZHdjL3BjaWUtaW14LmMKPiBpbmRleCBlOTMwNzBkNjBkZjUyLi43N2RhZTVjM2Y3MDU3 IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUtaW14LmMKPiAr KysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWlteC5jCj4gQEAgLTEwMyw2ICsx MDMsNyBAQCBzdHJ1Y3QgaW14X3BjaWVfZHJ2ZGF0YSB7Cj4gIAljb25zdCB1MzIgbW9kZV9tYXNr W0lNWF9QQ0lFX01BWF9JTlNUQU5DRVNdOwo+ICAJY29uc3Qgc3RydWN0IHBjaV9lcGNfZmVhdHVy ZXMgKmVwY19mZWF0dXJlczsKPiAgCWludCAoKmluaXRfcGh5KShzdHJ1Y3QgaW14X3BjaWUgKnBj aWUpOwo+ICsJaW50ICgqc2V0X3JlZl9jbGspKHN0cnVjdCBpbXhfcGNpZSAqcGNpZSwgYm9vbCBl bmFibGUpOwo+ICB9Owo+ICAKPiAgc3RydWN0IGlteF9wY2llIHsKPiBAQCAtNTg1LDc3ICs1ODYs NTQgQEAgc3RhdGljIGludCBpbXhfcGNpZV9hdHRhY2hfcGQoc3RydWN0IGRldmljZSAqZGV2KQo+ ICAJcmV0dXJuIDA7Cj4gIH0KPiAgCj4gLXN0YXRpYyBpbnQgaW14X3BjaWVfZW5hYmxlX3JlZl9j bGsoc3RydWN0IGlteF9wY2llICppbXhfcGNpZSkKPiArc3RhdGljIGludCBpbXg2c3hfcGNpZV9z ZXRfcmVmX2NsayhzdHJ1Y3QgaW14X3BjaWUgKmlteF9wY2llLCBib29sIGVuYWJsZSkKPiAgewo+ IC0JdW5zaWduZWQgaW50IG9mZnNldDsKPiAtCWludCByZXQgPSAwOwo+ICsJcmVnbWFwX3VwZGF0 ZV9iaXRzKGlteF9wY2llLT5pb211eGNfZ3ByLCBJT01VWENfR1BSMTIsIElNWDZTWF9HUFIxMl9Q Q0lFX1RFU1RfUE9XRVJET1dOLAo+ICsJCQkgICBlbmFibGUgPyAwIDogSU1YNlNYX0dQUjEyX1BD SUVfVEVTVF9QT1dFUkRPV04pOwo+ICAKPiAtCXN3aXRjaCAoaW14X3BjaWUtPmRydmRhdGEtPnZh cmlhbnQpIHsKPiAtCWNhc2UgSU1YNlNYOgo+IC0JCXJlZ21hcF91cGRhdGVfYml0cyhpbXhfcGNp ZS0+aW9tdXhjX2dwciwgSU9NVVhDX0dQUjEyLAo+IC0JCQkJICAgSU1YNlNYX0dQUjEyX1BDSUVf VEVTVF9QT1dFUkRPV04sIDApOwo+IC0JCWJyZWFrOwo+IC0JY2FzZSBJTVg2UVA6Cj4gLQljYXNl IElNWDZROgo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgaW14NnFfcGNpZV9z ZXRfcmVmX2NsayhzdHJ1Y3QgaW14X3BjaWUgKmlteF9wY2llLCBib29sIGVuYWJsZSkKPiArewo+ ICsJaWYgKGVuYWJsZSkgewo+ICAJCS8qIHBvd2VyIHVwIGNvcmUgcGh5IGFuZCBlbmFibGUgcmVm IGNsb2NrICovCj4gLQkJcmVnbWFwX3VwZGF0ZV9iaXRzKGlteF9wY2llLT5pb211eGNfZ3ByLCBJ T01VWENfR1BSMSwKPiAtCQkJCSAgIElNWDZRX0dQUjFfUENJRV9URVNUX1BELCAwIDw8IDE4KTsK PiArCQlyZWdtYXBfdXBkYXRlX2JpdHMoaW14X3BjaWUtPmlvbXV4Y19ncHIsIElPTVVYQ19HUFIx LCBJTVg2UV9HUFIxX1BDSUVfVEVTVF9QRCwgMCk7Cj4gIAkJLyoKPiAtCQkgKiB0aGUgYXN5bmMg cmVzZXQgaW5wdXQgbmVlZCByZWYgY2xvY2sgdG8gc3luYyBpbnRlcm5hbGx5LAo+IC0JCSAqIHdo ZW4gdGhlIHJlZiBjbG9jayBjb21lcyBhZnRlciByZXNldCwgaW50ZXJuYWwgc3luY2VkCj4gLQkJ ICogcmVzZXQgdGltZSBpcyB0b28gc2hvcnQsIGNhbm5vdCBtZWV0IHRoZSByZXF1aXJlbWVudC4K PiAtCQkgKiBhZGQgb25lIH4xMHVzIGRlbGF5IGhlcmUuCj4gKwkJICogdGhlIGFzeW5jIHJlc2V0 IGlucHV0IG5lZWQgcmVmIGNsb2NrIHRvIHN5bmMgaW50ZXJuYWxseSwgd2hlbiB0aGUgcmVmIGNs b2NrIGNvbWVzCj4gKwkJICogYWZ0ZXIgcmVzZXQsIGludGVybmFsIHN5bmNlZCByZXNldCB0aW1l IGlzIHRvbyBzaG9ydCwgY2Fubm90IG1lZXQgdGhlCj4gKwkJICogcmVxdWlyZW1lbnQuYWRkIG9u ZSB+MTB1cyBkZWxheSBoZXJlLgoKUGxlYXNlIHdyYXAgdGhlIGNvbW1lbnRzIHRvIDgwIGNvbHVt biB3aWR0aC4KCj4gIAkJICovCj4gIAkJdXNsZWVwX3JhbmdlKDEwLCAxMDApOwo+ICAJCXJlZ21h cF91cGRhdGVfYml0cyhpbXhfcGNpZS0+aW9tdXhjX2dwciwgSU9NVVhDX0dQUjEsCj4gLQkJCQkg ICBJTVg2UV9HUFIxX1BDSUVfUkVGX0NMS19FTiwgMSA8PCAxNik7Cj4gLQkJYnJlYWs7Cj4gLQlj YXNlIElNWDdEOgo+IC0JY2FzZSBJTVg5NToKPiAtCWNhc2UgSU1YOTVfRVA6Cj4gLQkJYnJlYWs7 Cj4gLQljYXNlIElNWDhNTToKPiAtCWNhc2UgSU1YOE1NX0VQOgo+IC0JY2FzZSBJTVg4TVE6Cj4g LQljYXNlIElNWDhNUV9FUDoKPiAtCWNhc2UgSU1YOE1QOgo+IC0JY2FzZSBJTVg4TVBfRVA6Cj4g LQkJb2Zmc2V0ID0gaW14X3BjaWVfZ3JwX29mZnNldChpbXhfcGNpZSk7Cj4gLQkJLyoKPiAtCQkg KiBTZXQgdGhlIG92ZXIgcmlkZSBsb3cgYW5kIGVuYWJsZWQKPiAtCQkgKiBtYWtlIHN1cmUgdGhh dCBSRUZfQ0xLIGlzIHR1cm5lZCBvbi4KPiAtCQkgKi8KPiAtCQlyZWdtYXBfdXBkYXRlX2JpdHMo aW14X3BjaWUtPmlvbXV4Y19ncHIsIG9mZnNldCwKPiAtCQkJCSAgIElNWDhNUV9HUFJfUENJRV9D TEtfUkVRX09WRVJSSURFLAo+IC0JCQkJICAgMCk7Cj4gLQkJcmVnbWFwX3VwZGF0ZV9iaXRzKGlt eF9wY2llLT5pb211eGNfZ3ByLCBvZmZzZXQsCj4gLQkJCQkgICBJTVg4TVFfR1BSX1BDSUVfQ0xL X1JFUV9PVkVSUklERV9FTiwKPiAtCQkJCSAgIElNWDhNUV9HUFJfUENJRV9DTEtfUkVRX09WRVJS SURFX0VOKTsKPiAtCQlicmVhazsKPiArCQkJCSAgIElNWDZRX0dQUjFfUENJRV9SRUZfQ0xLX0VO LCBJTVg2UV9HUFIxX1BDSUVfUkVGX0NMS19FTik7Cj4gKwl9IGVsc2Ugewo+ICsJCXJlZ21hcF91 cGRhdGVfYml0cyhpbXhfcGNpZS0+aW9tdXhjX2dwciwgSU9NVVhDX0dQUjEsCj4gKwkJCQkgICBJ TVg2UV9HUFIxX1BDSUVfUkVGX0NMS19FTiwgMCk7Cj4gKwkJcmVnbWFwX3VwZGF0ZV9iaXRzKGlt eF9wY2llLT5pb211eGNfZ3ByLCBJT01VWENfR1BSMSwKPiArCQkJCSAgIElNWDZRX0dQUjFfUENJ RV9URVNUX1BELCBJTVg2UV9HUFIxX1BDSUVfVEVTVF9QRCk7Cj4gIAl9Cj4gIAo+IC0JcmV0dXJu IHJldDsKPiArCXJldHVybiAwOwo+ICB9Cj4gIAo+IC1zdGF0aWMgdm9pZCBpbXhfcGNpZV9kaXNh YmxlX3JlZl9jbGsoc3RydWN0IGlteF9wY2llICppbXhfcGNpZSkKPiArc3RhdGljIGludCBpbXg4 bW1fcGNpZV9zZXRfcmVmX2NsayhzdHJ1Y3QgaW14X3BjaWUgKmlteF9wY2llLCBib29sIGVuYWJs ZSkKPiAgewo+IC0Jc3dpdGNoIChpbXhfcGNpZS0+ZHJ2ZGF0YS0+dmFyaWFudCkgewo+IC0JY2Fz ZSBJTVg2UVA6Cj4gLQljYXNlIElNWDZROgo+IC0JCXJlZ21hcF91cGRhdGVfYml0cyhpbXhfcGNp ZS0+aW9tdXhjX2dwciwgSU9NVVhDX0dQUjEsCj4gLQkJCQlJTVg2UV9HUFIxX1BDSUVfUkVGX0NM S19FTiwgMCk7Cj4gLQkJcmVnbWFwX3VwZGF0ZV9iaXRzKGlteF9wY2llLT5pb211eGNfZ3ByLCBJ T01VWENfR1BSMSwKPiAtCQkJCUlNWDZRX0dQUjFfUENJRV9URVNUX1BELAo+IC0JCQkJSU1YNlFf R1BSMV9QQ0lFX1RFU1RfUEQpOwo+IC0JCWJyZWFrOwo+IC0JY2FzZSBJTVg3RDoKPiAtCQlyZWdt YXBfdXBkYXRlX2JpdHMoaW14X3BjaWUtPmlvbXV4Y19ncHIsIElPTVVYQ19HUFIxMiwKPiAtCQkJ CSAgIElNWDdEX0dQUjEyX1BDSUVfUEhZX1JFRkNMS19TRUwsCj4gLQkJCQkgICBJTVg3RF9HUFIx Ml9QQ0lFX1BIWV9SRUZDTEtfU0VMKTsKPiAtCQlicmVhazsKPiAtCWRlZmF1bHQ6Cj4gLQkJYnJl YWs7Cj4gLQl9Cj4gKwlpbnQgb2Zmc2V0ID0gaW14X3BjaWVfZ3JwX29mZnNldChpbXhfcGNpZSk7 Cj4gKwo+ICsJLyogU2V0IHRoZSBvdmVyIHJpZGUgbG93IGFuZCBlbmFibGVkIG1ha2Ugc3VyZSB0 aGF0IFJFRl9DTEsgaXMgdHVybmVkIG9uLiovCj4gKwlyZWdtYXBfdXBkYXRlX2JpdHMoaW14X3Bj aWUtPmlvbXV4Y19ncHIsIG9mZnNldCwgSU1YOE1RX0dQUl9QQ0lFX0NMS19SRVFfT1ZFUlJJREUs Cj4gKwkJCSAgIGVuYWJsZSA/IDAgOiBJTVg4TVFfR1BSX1BDSUVfQ0xLX1JFUV9PVkVSUklERSk7 Cj4gKwlyZWdtYXBfdXBkYXRlX2JpdHMoaW14X3BjaWUtPmlvbXV4Y19ncHIsIG9mZnNldCwgSU1Y OE1RX0dQUl9QQ0lFX0NMS19SRVFfT1ZFUlJJREVfRU4sCj4gKwkJCSAgIGVuYWJsZSA/IElNWDhN UV9HUFJfUENJRV9DTEtfUkVRX09WRVJSSURFX0VOIDogIDApOwoKRXh0cmEgc3BhY2UgYWZ0ZXIg OgoKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IGlteDdkX3BjaWVfc2V0X3Jl Zl9jbGsoc3RydWN0IGlteF9wY2llICppbXhfcGNpZSwgYm9vbCBlbmFibGUpCj4gK3sKPiArCXJl Z21hcF91cGRhdGVfYml0cyhpbXhfcGNpZS0+aW9tdXhjX2dwciwgSU9NVVhDX0dQUjEyLCBJTVg3 RF9HUFIxMl9QQ0lFX1BIWV9SRUZDTEtfU0VMLAo+ICsJCQkgICAgZW5hYmxlID8gMCA6IElNWDdE X0dQUjEyX1BDSUVfUEhZX1JFRkNMS19TRUwpOwo+ICsJcmV0dXJuIDA7Cj4gIH0KPiAgCj4gIHN0 YXRpYyBpbnQgaW14X3BjaWVfY2xrX2VuYWJsZShzdHJ1Y3QgaW14X3BjaWUgKmlteF9wY2llKQo+ IEBAIC02NjgsMTAgKzY0NiwxMiBAQCBzdGF0aWMgaW50IGlteF9wY2llX2Nsa19lbmFibGUoc3Ry dWN0IGlteF9wY2llICppbXhfcGNpZSkKPiAgCWlmIChyZXQpCj4gIAkJcmV0dXJuIHJldDsKPiAg Cj4gLQlyZXQgPSBpbXhfcGNpZV9lbmFibGVfcmVmX2NsayhpbXhfcGNpZSk7Cj4gLQlpZiAocmV0 KSB7Cj4gLQkJZGV2X2VycihkZXYsICJ1bmFibGUgdG8gZW5hYmxlIHBjaWUgcmVmIGNsb2NrXG4i KTsKPiAtCQlnb3RvIGVycl9yZWZfY2xrOwo+ICsJaWYgKGlteF9wY2llLT5kcnZkYXRhLT5zZXRf cmVmX2Nsaykgewo+ICsJCXJldCA9IGlteF9wY2llLT5kcnZkYXRhLT5zZXRfcmVmX2NsayhpbXhf cGNpZSwgdHJ1ZSk7Cj4gKwkJaWYgKHJldCkgewo+ICsJCQlkZXZfZXJyKGRldiwgInVuYWJsZSB0 byBlbmFibGUgcGNpZSByZWYgY2xvY2tcbiIpOwoKJ0ZhaWxlZCB0byBlbmFibGUgUENJZSBSRUZD TEsnCgotIE1hbmkKCi0tIArgrq7grqPgrr/grrXgrqPgr43grqPgrqngr40g4K6a4K6k4K6+4K6a 4K6/4K614K6u4K+NCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3Rz LmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5m by9saW51eC1hcm0ta2VybmVsCg==